Does a synchronous shift register put out its result at the same time as it gets its input, or does it output it at the next rising edge?
\$\begingroup\$
\$\endgroup\$
5
asked May 20, 2011 at 13:25
-
2\$\begingroup\$ are you talking about a serial-in, serial-out shift register, or a serial-in, parallel-out one? \$\endgroup\$– DaveMay 20, 2011 at 13:31
-
\$\begingroup\$ What's the difference, and does it make a difference? \$\endgroup\$– 200ok404notfoundMay 20, 2011 at 13:46
-
1\$\begingroup\$ Give a device reference, so that we can check a data sheet. \$\endgroup\$– Leon HellerMay 20, 2011 at 14:11
-
\$\begingroup\$ serial-in serial-out will time delay all of the data you are clocking in. serial-in parallel-out will output all of the data you clocked in at once on a parallel data bus. I have used the latter to drive things like LED segments, or any time I don't have enough I/O available. \$\endgroup\$– DaveMay 20, 2011 at 14:24
-
\$\begingroup\$ So basically, the serial-in parallel-out register is asynchronous. \$\endgroup\$– 200ok404notfoundMay 20, 2011 at 14:39
Add a comment
|
4 Answers
\$\begingroup\$
\$\endgroup\$
2
Normally the outputs of a Synchronous Shift Register will change in response to a clock edge. Of course the exact details will depend on exactly what shift register you're trying to use.
-
\$\begingroup\$ If I simulate sending commands to a shift register right at the rising edge, the shift register doesn't respond. I have to start the command before the rising edge and leave it on during the rising edge for it to be recognized. Why is that? \$\endgroup\$ May 20, 2011 at 14:51
-
\$\begingroup\$ @2000k404notfound Sounds like you need to understand what setup and hold time is. Here's a link: en.wikipedia.org/wiki/… \$\endgroup\$– user3624May 20, 2011 at 15:00
\$\begingroup\$
\$\endgroup\$
There are two common shift register designs with regard to the shift inputs and outputs. On some shift registers, the shift-input sampling and shift-output change happen on the same clock edge; on others, they happen on opposite clock edges. Generally, it's better for the sampling and change to happen on opposite clock edges unless it can be guaranteed that the recipient of the data will receive the clock before the sender does (e.g. because the data recipient is generating the clock).
From what I can tell, it seems a lot of logic is implemented on the principle that all inputs and outputs change on the same clock edge, though I would tend to think that in many cases it would be better to use opposite clock edges. If everything uses the same clock edge, clock matching is critical, even at clock rates down to DC. By contrast, if outputs change on one edge and inputs are sampled on another, clock rates may not be able to go as fast as when using one edge for everything, but clock skew will merely limit the top usable clock speed, rather than rendering the device unusable at any speed.
\$\begingroup\$
\$\endgroup\$
1
It depends on the device you are using.
However, it will never be "at the same time". Nothing happens in zero amount of time.
Your device datasheet will have the information you need. For example...
Datasheet: 74HC595: 8-Bit Shift Register w/Output Storage Register (3-State)
Sections of interest in the datasheet
- Function Table
- Timing Requirements
- Timing Diagram
- Switching Waveforms
From this data we can determine things like...
- Data is shifted into the register on a rising edge of the shift clock.
- The serial input must be present for tsu before switch clock goes high (fiq.5).
- tsu is in nanoseconds.
- tsu could be as long as 75ns depending on Vcc and temperature.
- And more...
-
\$\begingroup\$ One nasty gotcha with something like a 74xx595 is that there's no specification that guarantees that the output from one 74HC595 won't change fast enough in response to the clock to violate the setup time for a succeeding 74HC595. In practice, chips which have longer setup times are also apt to have longer propagation delays, so if the source and destination chip are of the same family things will generally work. Still, I think it's a bit icky to have the output change on the same edge as the input. \$\endgroup\$– supercatMay 21, 2011 at 2:40
\$\begingroup\$
\$\endgroup\$
In addition to David Kessner's answer, some serial-in-parallel-out shift registers have an Output Latch Enable. This allows you to shift e.g. 8 bits into the shift register without the inputs "sliding" across the output. Once you get all your bits in, then you assert OLE during a clock edge, and all 8 output bits are updated simultaneously.
