Does a synchronous shift register put out its result at the same time as it gets its input, or does it output it at the next rising edge?
There are two common shift register designs with regard to the shift inputs and outputs. On some shift registers, the shift-input sampling and shift-output change happen on the same clock edge; on others, they happen on opposite clock edges. Generally, it's better for the sampling and change to happen on opposite clock edges unless it can be guaranteed that the recipient of the data will receive the clock before the sender does (e.g. because the data recipient is generating the clock).
From what I can tell, it seems a lot of logic is implemented on the principle that all inputs and outputs change on the same clock edge, though I would tend to think that in many cases it would be better to use opposite clock edges. If everything uses the same clock edge, clock matching is critical, even at clock rates down to DC. By contrast, if outputs change on one edge and inputs are sampled on another, clock rates may not be able to go as fast as when using one edge for everything, but clock skew will merely limit the top usable clock speed, rather than rendering the device unusable at any speed.
It depends on the device you are using.
However, it will never be "at the same time". Nothing happens in zero amount of time.
Your device datasheet will have the information you need. For example...
Sections of interest in the datasheet
- Function Table
- Timing Requirements
- Timing Diagram
- Switching Waveforms
From this data we can determine things like...
- Data is shifted into the register on a rising edge of the shift clock.
- The serial input must be present for tsu before switch clock goes high (fiq.5).
- tsu is in nanoseconds.
- tsu could be as long as 75ns depending on Vcc and temperature.
- And more...
In addition to David Kessner's answer, some serial-in-parallel-out shift registers have an Output Latch Enable. This allows you to shift e.g. 8 bits into the shift register without the inputs "sliding" across the output. Once you get all your bits in, then you assert OLE during a clock edge, and all 8 output bits are updated simultaneously.