0
\$\begingroup\$

I have designed a CMOS op-amp circuit like figure

enter image description here

The problem is the phase margin is 79. How can I decrease phase margin to 60?

\$\endgroup\$
2
  • \$\begingroup\$ try to think: what components contribute to the dominant pole frequency? what components contribute to the higher frequency poles? to decrease PM you either move the dominant pole UP or you move the HHFF poles DOWN. Probably the latter is simpler and is only about inserting a tiny cap somewhere. \$\endgroup\$ Dec 24, 2014 at 8:58
  • 3
    \$\begingroup\$ Why is a phase margin of 79 deg "a problem"? \$\endgroup\$
    – LvW
    Dec 24, 2014 at 9:12

1 Answer 1

1
\$\begingroup\$

It is difficult to comment on the exact change required to get the desired phase margin as that would depend on the design specifications and chosen values for the components. I will try to provide helpful pointers that can help you attain required phase margin values.

For a two pole system, for a phase margin of 60 degrees, the unity gain bandwidth should be 1.73*fp2.However, the unity gain bandwidth is determined by the dc gain and the first pole, fp1. UGB= Av|dc * fp1.

This provides us with two direct ways of controlling the phase margin 1. Changing fp2 according to the UGB 2. Changing the UGB according to fp2 a. By changing the dc gain b. By changing the first pole frequency

By identifying which nodes each of the first and the second pole correspond to, it should be fairly straightforward to identify the cicrcuit parameter that needs to be tweaked. While implementing each of these methods, you should also carefully consider the trade-off and see which parameter you can most easily trade off. There would most likely be specifications for dc gain and bandwidth requirements, and if those are not things you want to trade, you'll have to go for the pole frequencies.

But before you change anything in the circuit, it is important to ensure that you even require the 60 degrees! Even a 79 degree phase margin would keep your amplifier away from ringing, and a larger phase margin implies greater stability. At the same time, when you run corners and test the circuit across a range of PVT variations, the phase margin would not hold at the nominal or worst case value. Therfore, it is probably better to just ensure that the worst case PM is above 60 degrees or or 45 degrees.

PS-using labels for nets in Cadence will save you from physically drawing wires between connected nodes and would make your circuit easier to understand and debug. The keyboard shortcut is L.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.