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I'm studying basic opamp configurations and was trying to determine which configuration was used in this battery simulator. Its schematic is below.

Battery simulator circuit schematic

The circuit description, from this application note, is below:

In charge mode, current is forced through the battery input terminals. The low voltage that develops across R8 is amplified by U1 and causes Q1 to shunt the charge current while maintaining the power supply PS1 voltage.

Since the small current through R8 must come from right to left, the voltage on the non-inverting opamp input (+) must be higher than the voltage on the inverting input (-) for the opamp to turn Q1 on. That requires a positive output, leading me to conclude that the opamp is wired in the non-inverting config.

But the non-inverting (+) terminal is also connected to both the PS1 and the voltage regulator LT1073 ground terminals, leading me to believe that the opamp is in the inverting configuration, as in Figure 3 below.

So, in which configuration is this opamp really set up?

Non-inverting OpAmp configuration

Figure 2: Non-inverting OpAmp configuration

Inverting OpAmp configuration

Figure 3: Inverting OpAmp configuration

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It's not in either of those modes, but it's being used as a differential amplifier:

enter image description here

It doesn't amplify a single signal, either inverting or non-inverting - it amplifies the difference between two signals - in this case the difference in voltage between the two sides of R8.

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U1 is being used as a current sense amplifier. It's topology is a non-inverting integrator. Of the two example circuits you show, it is most like the non-inverting configuration, with R2 of your Figure 2 being replaced by series combination of R4 and C2. You can tell it's non-inverting topology because R5 references the return of U1 directly, while R6 does not.

As an integrator it will have DC gain that is as high as the OpAmp can manage, which for the LT1078 is ~120dB, a pole at zero frequency so that gain falls off by 20dB/decade, and a zero at ~160Hz so that the gain flattens out at ~21dB. One must suppose that whoever designed this circuit found that having a zero at 160Hz would stabilize the loop controlling Q1 while active.

When in charge mode U1-3 will be positive and the output U1-1 will be positive to cause Q1 to be active and shunt current back to the charging return. When in discharge mode U1-3 will be negative and U1-1 will be as low as it can be so that Q1 is inactive.

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