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Is the naming of the two flash architectures related to differences between the two types of logic gates? If so, how?

Why does or doesn't this difference also apply to different DRAM or SRAM configurations or layouts?

(This question is not about the R/W performance or usage differences between NAND and NOR flash, which has already been asked here: What are the differences between NAND and NOR flash? )

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Because they're wired like a NAND or NOR gate. (See this question for classical CMOS NAND/NOR gates. Here the logic is just NMOS 'pull-down', not CMOS)

NAND vs NOR memory cells

To read NAND flash, every transistor is switched on in the cell except the one being read. Because it's wired like a NAND gate, where if every signal is AND'ed you get a low, if you see a low on the bit line then you know the memory cell was set.

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NAND flash has groups of flash transistors in series, like a NAND gate. This saves some die area since you can connect them source -> drain without needing contacts or metal. NOR flash has the flash transistors in parallel.

I won't go into the mechanics of reads unless you want me to, but the upshot is that NOR flash is designed to be random access, meaning any address can be read with the same access time. NAND flash is designed to be read in blocks.

The reason this doesn't apply to DRAM and SRAM is that RAMs are always designed to be random access. (Hence the name, I suppose.) access time is more important for main memory than for nonvolatile storage. (I'm not sure if you could even make NAND-style DRAM or SRAM. How would such a design work with non-floating gate transistors?)

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  • \$\begingroup\$ With large L2 or L3 cache, it seems plausible that NAND-style sequential access for main memory might make sense... \$\endgroup\$ – R.. Nov 30 '17 at 16:53

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