I am routing a PCB with an Ethernet connection and I am having a bit of trouble deciding on how best to route the TX and RX differential pairs. I have done the impedance calculations to figure out the track geometry needed for 100 ohm differential impedance and confirmed it with the board house. However, I have a bit of a length mismatch between the TX+/TX- and RX+/RX- pairs (about 5mm). Hence, I am employing the "squiggly line technique" to minimize the length mismatch of the traces in a pair.

My question is whether there is a rule of thumb or a precise calculation to figure out the squiggly line geometry? To illustrate what I mean, have a look at the attachment - I have routed one pair with "loose" squiggles (labelled 1. in the image) and another pair with "tight" squiggles (labelled 2, in the image). Which one is better and does it matter at all? My concern with the "tight squiggles" is degrading signal quality due to reflections as the squiggles are close to 90 degree angles which most app notes strongly advise against. The "loose squiggles" on the other hand take up more space and hence am I degrading my differential impedance?

Thanks and happy holidays! -Igor

enter image description here


I'm not sure where you have read that the squiggle design is used for this purpose, i.e. path length matching. From what I can find the only place where a squiggle (like the one you've drawn) is intentionally used in RFID squiggle antennas; and you probably don't want to build one of those on your board!

Below is an example of path length matching from a book I've read (Jacob et al. Memory Systems). There are one or two squiggly looking paths there but only with one or two periods at the most. The pattern shown there seems to prefer a high amplitude of the "squiggle" so that it has a low number of periods/repetitions. Most other routes shown there are lengthened in some way but not by squiggles. The most common lengthening method used there seems to be making pentagonal U-turns (a term I just made up because I don't know an established one) so that an exterior polyline is naturally longer than an interior one. I don't know what software is used to generate those designs (but it's a good question).

enter image description here

After more searching, it seems that a trade term for the squiggles when applied to trace length matching is "serpentine traces".

And I found an article discussing those: A New Slant on Matched-Length Routing by Barry Olney... Well, the article is actually about proposing an alternative to serpentines, but it does have some background before it gets to comparison. It does seem to me however that the very long serpentines shown in that article are for demonstrative/contrast purposes. I've seen at least two dozen network card models up closely in my computing life (in 20+ years) and I cannot remember noticing a pronounced squiggle like yours (or the one in that article) on any of their PCBs... Now it may have existed in the inner layers (on the few boards that had more than two) where it was not visible. Some cards do route their differential signals on the inner layers, as microstrip.

With this serpentine terminology, it turned out they are standard textbook subject. Thierauf's Understanding Signal Integrity book has a couple of pages on this. Alternative terms are (according to that textbook): "meander or trombone traces". If I get this right, the number of periods is to be minimized because each contributes to a ladder-like waveform created by crosstalk between the U-turns, as excerpted below from the aforementioned textbook. This is alas a purely theoretical analysis. enter image description here.

The book also says that this is only an approximative solution and that a "3D field solver" is needed to fully simulate the real behavior; for example, the signal actually propagates faster in a serpentine than the 2D trace length would indicate. I intuited correctly the recommendation the book was going to draw from that graph; quoting it below:

Because the maximum coupled voltage grows with the number of segments in the serpentine, when laying out a serpentine, it is best to use a fewer number of long segments instead of a greater number of short ones. Fewer segments also mean fewer corners and less uncertainty in the timing and impedance. For these reasons the segments should be long (typically greater than the signal rise time) and few in number. Also, because crosstalk increases as the traces are tightly packed together, laddering can be reduced by increasing the separation between segments.

Finally, the book also mentions placing a grounded guard trace between segments in a serpentine to (further) reduce laddering caused by crosstalk. The book also lists/cites a few more in-depth papers on this serpentine issue:

  • Wu, R., and F. Chao, “Laddering Wave in Serpentine Delay Line,” IEEE Transactions on Components, Packaging, and Manufacturing Technology, Part B, Vol. 18, No. 4, November 1995, pp. 644–650.
  • Rubin, B. J., and B. Singh, “Study of Meander Line Delay in Circuit Boards,” IEEE Transactions on Microwave Theory and Techniques, Vol. 48, No. 9, September 2000, pp. 1452–1460.
  • Orhanovic, N., et al., “Characterization of Microstrip Meanders in PCB Interconnects,” Proceedings 50th IEEE Electronic Components and Technology Conference, Las Vegas, NV, May 21–24, 2000, pp. 508–512.
  • Shiue, G., et al., “Improvements of Time-Domain Transmission Waveform in Serpentine Delay Line with Guard Traces,” IEEE International Symposium on Electromagnetic Compatibility, EMC 2007, Honolulu, HI, July 9–13, 2007, pp. 1–5.
  • Nara, S., and K. Koshiji, “Study on Delay Time Characteristics of Multilayered Hyper- Shielded Meander Line,” IEEE International Symposium on Electromagnetic Compatibility, EMC 2006, Vol. 3, Portland, OR, August 14–18, 2006, pp. 760–763.

On a more practical note, NXP has an app note DisplayPort PCB layout guidelines (AN10798) that touches on several aspects of trace lenght mathcing on pp. 4-6. They recommend the serpentine design shown below, which also obeys other rules, like not allowing too much distance between differential pairs.

enter image description here

  • \$\begingroup\$ Thanks Respawned Fluff. I have encountered these serpentine traces quite often, especially if you look at connections between a CPU and memory. My particular concern are Ethernet traces I am routing. I have 50mm of traces and the pairs are mismatched by 5mm (i.e. 5mm length difference between TX+ and TX- due to routing around the RJ45 connector). Do you reckon I should bother with serpentines at all or just route straight as differential pairs as length mismatch is at most 5mm? \$\endgroup\$ – IgorEE Jan 4 '15 at 16:17
  • \$\begingroup\$ Well, you're not even saying what speed of Ethernet (100Mbp, 1Gbps; I assume it's not 10Gbps because you mentioned RJ45). There are (expensive!) commercial simulators such as HyperLynx that can answer such questions in detail. I have not personally designed any Ethernet cards, so I can't say off the top of my head. But assuming this is 1Gbps, you can probably learn from the Intel design e.g. intel.com/content/dam/www/public/us/en/documents/design-guides/… Looking briefly at that 5mm sounds like a lot, so you should probably compensate. \$\endgroup\$ – Fizz Jan 4 '15 at 16:59
  • \$\begingroup\$ Sorry about that, it is 100Mbp Ethernet so perhaps that 5mm ia not too bad? I'll have a look at that Intel design. \$\endgroup\$ – IgorEE Jan 4 '15 at 17:05
  • \$\begingroup\$ Possibly. Intel says to match MDI pairs within 30 mils at gigabit. I suppose 300 mils (=7.62mm) would be okay at 100Mbps; but I could be wrong. Also, it's not very clear if you're talking about within-pairs or between-pairs length matching. The latter is less critical; even at Gigabit Intel allows two inches mismatch between pairs (but only 30 mils within pairs). They also say to avoid serpentines for MDI (while they allow them for PCIe) because of increased EMI (with cable attached) and, interestingly, also because serpentines decrease ESD immunity. \$\endgroup\$ – Fizz Jan 4 '15 at 17:41
  • \$\begingroup\$ The mismatch is within pairs, I am aware that the mismatch between the two pairs is not as critical. I just had a look at the routing of the raspberryPi model B+ as this is a design I am loosely copying, and they also have serpentines on the ethernet lines as on my design above, so I guess length matching is also important in addition to maintaining differential impedance. I was hoping there would be some rule of thumb as to serpentine shape design but apparently besides comparison of tight and loose serpentines as mentioned above, there is no rule and it seems a proper EM solver would be... \$\endgroup\$ – IgorEE Jan 4 '15 at 18:18

Your bigger concern with tight squiggles is that part of your signal can couple right through them and end up coming out the other side sooner than you think. Best to use larger like your first drawing.

Also keep the squiggles close to either your transmitter, receiver or connector. Perhaps less than 1/4 wavelength of the highest frequency content of interest away from your transmitter. Best to lump discontinuities together.


Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.