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I am studying the PowerPC architecture on the MPC5644B. The documents from Freescale mention it to be a single Issue architecture.

The data sheet states the following,

• e200z0h single issue, 32-bit core Power
Architecture compliant CPU
— Up to 80 MHz
— Variable length encoding (VLE)
— Supports Nexus3+

I did some Google search and read forums, this seems to be some kind of Mixed Harvard architecture, but i am not sure exactly what it is. If anyone could help , it would be highly apprecieated.

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A single issue processor is basically one instruction, one clock cycle.

Every clock cycle one thing happens. In a pipelined processor basically that means the pipeline gets shifted down a notch and a new instruction is read from memory. That of course is at its most efficient. Some instructions may take longer that one clock cycle to execute, so the pipeline would stall. But assuming all the instructions take just one clock cycle to execute, then for every clock tick you read just one instruction from memory.

That, at its most efficient, is called having "A CPI of 1", or "One Clock per Instruction".

That basically covers the majority of normal CPUs.

Now imagine a CPU which can execute two instructions for each clock tick - say one on the rising edge and one on the falling edge of the clock. So for each tick of the clock you're running 2 instructions, fetching 2 instructions from memory, etc. This is called dual issue since it's issuing two instructions per clock tick.

In this situation it's possible to get a CPI of 0.5, or half a clock tick per instruction.

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  • \$\begingroup\$ Instructions that take longer than one cycle to execute do not necessarily stall the pipeline. Even if the particular operation is not pipelined (e.g., as is not uncommon for division), other operations are usually allowed to issue until an operation dependent on the result of the long-latency operation is reached. Also, dual issue typically begins execution of two operations in parallel not in half-cycles. (Incidentally, the types of operations supported for parallel issue are usually constrained, excluding parallel execution of 2 "expensive" operations of the same kind, e.g., 2 loads.) \$\endgroup\$ – Paul A. Clayton Dec 26 '14 at 18:02
  • \$\begingroup\$ That's all very well, but none of that has any bearing on the question. The question is not how does dual issue work, but what is the difference between dual and single issue. The mechanics behind it at this stage are completely irrelevant. There are different ways dual issue could be implemented - I just made up a simple one for illustrative purposes. \$\endgroup\$ – Majenko Dec 26 '14 at 18:04
  • \$\begingroup\$ I agree it does not bear on the question, but less accurate information is problematic. Something like "at its most efficient; various hazards can cause the pipeline to stall, increasing the cycles per instruction (CPI)." is more accurate and concise and albeit a little less accessible (not ideal for the OP). "say one ...of the clock" seems to add little if any real value and could easily lead a reader to think that such is the typical way dual issue is implemented. \$\endgroup\$ – Paul A. Clayton Dec 26 '14 at 18:30
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Single issue simply means that the CPU is not "superscalar", it cannot execute more than 1 instruction per cycle.

The Single/multiple issue aspect is independant from the idea that the CPU may have a shared instruction/data bus or have separate ones (a.k.a. Harvard), or feature in-order or out-of-order execution.

The MPC5644B has only one CPU core, a superscalar dual issue e200z4d PowerPC core, whereas the MPC5644C has both a e200z4d and a e200z0h (which is single issue) core on-chip.

Anyway, look at the Freescale datasheets "MPC564xB-C: Qorivva 32-bit MCU for Body Control Module and Gateway Applications".

http://cache.freescale.com/files/microcontrollers/doc/fact_sheet/MPC564XBCFS.pdf?fpsp=1

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