I‘m new here and have the following problem. I have developed a module in vhdl which scales the frequency of an input clk by the input prescaling value (0-255) s.t. the frequency of the output signal is f_out=f_in/(1+prescale).
My design works fine in simulation but from past uni courses and eyperience I know this is still far from working in hardware.
What I believe might cause a problem is the following: I have an internal signal that switches level when a rising edge for clk_out should occur and one which switches level when a falling edge for clk_out should occur. clk_out is then simply an XOR of both...so behind these two buffered internal signals I have a small combinatorial part that generates clk_out. My design keeps the duty cycle at 50% so a falling edge can be generated at a falling edge of clk_in, thus I cant simply flop clk_out.
So my questions are:
- Will the combinatorial part cause problems in an fpga design? Afterall...clk_out will be used as a cloxk signal.
- Is there perhaps a better way to approach this? I really only need the rising edge of clk_out so the duty cycle is not too crutial, however how will.I realize the clk_in=clk_out case?