This question is derived from this question after additional experimenting how to avoid power up and power down overshoot with or without load connected to power supply. With my present level of knowledge I resolve this issue effectively using the following circuit (see "dashed" frame section):


It's very simple: LM555 is used for power up delay until bias supply (+/-15 for CC and CV logic) is stabilized as shown below (Vout=yellow, +15V=magenta, -15V=blue).

Power up condition

When power is switched off, then relay is demagnetized while valid bias (+/-15V) is still present and make clean cut by connecting the gate to the ground and no overshoot in CV mode is present. That is nicely visible on the following image:

Power down condition

So far so good. My question is: since this solution with relay is a little too "mechanical" is there a replacement for such functionality?

I spent some time experimenting with MOSFET and BJT as a switch but the problem is that we are working here with marginal situations where power for the switch is also coming in and going away. I found some workable solution for power up case but "grounding" Q1 gate in case of power down to inhibit any residual control voltage what results in appearing undesired (uncontrolled) DCIN to the OUT+ is beyond my expertise.

EDIT 2015-02-26: I spent some time to use different type of bias supply with proper power sequencing. That made this question and one from which this one is derived not relevant anymore. Used solution is mentioned here and here.

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    \$\begingroup\$ You could use a solid state relay as a replacement - they're expensive, but they're basically an optocoupled triac. \$\endgroup\$ – Mister Mystère Jan 31 '15 at 22:01

Option 2: Replace the analog circuit with a microcontroller


simulate this circuit – Schematic created using CircuitLab

Without external input, pull-down R1 firmly applies ground to Vgate through Q2.

(Existing)R2 is large-ish since FET gate does not need large current.

R3 is current protection for the LED inside the opto. A 380ohm resistor with a 1.2V drop across the LED yields about 10mA.

When uC_PowerEnable becomes high, Q2's gate is biased at DCIN, allowing Vgate to rise.

The recommended capacitor across the ATTiny power supply pins can be up-sized to ensure the Tiny is the last thing that turns off. Without signal from the uC, R1 resumes its original role of 'permanently' grounding Vgate. In this setup, the uC can shut down Vout for any reason(s) and can be reprogrammed, instead of redesigned and/or resoldered.

SetPin(uC_PowerEnable, VinPlus15Good && VinMinus15Good); //Shut down if either input rail fails
  • \$\begingroup\$ Tested with BC640 and applying 0 or +5V to the uC_PowerEnable input. With 0V Vout+ (Q1 Source pin) goes to 0V what is good, but with +5V it also goes down to +2.3V. \$\endgroup\$ – prasimix Feb 1 '15 at 10:52
  • \$\begingroup\$ Revised schematic using opto to simplify dual voltage design. If you have a separate DGND and AGND, you should ground the LED to DGND. \$\endgroup\$ – Jon Feb 4 '15 at 23:29
  • \$\begingroup\$ As a matter of fact, uC_PowerEnable could be connected to the input side of R2. R3 would need to be up-sized to protect the LED from the increased voltage. I'm going to replace my option 1 schematic to reflect that. \$\endgroup\$ – Jon Feb 4 '15 at 23:40
  • \$\begingroup\$ I surmise that existing R1 was added to protect the IRF. Since FETs respond to voltage rather than current, consider attaching my circuit (@Vgate) to the GATE-side of existing R1 instead of the ZD1-side. That should give proposed Q2 an easier time grounding any voltage coming back through ZD1. The gate will pull easily to 0V, regardless of load, since R1 will help eat up some the difference. You may or may not need to up-size existing R1 after moving it. \$\endgroup\$ – Jon Feb 5 '15 at 2:14

Option 1) Remain analog


simulate this circuit – Schematic created using CircuitLab

With DCIN applied, the opto-isolator is activated and conducts DCIN to the gate of Q2, switching it off, and allowing Vgate to rise.

When DCIN is disconnected, the opto blocks and R6 biases Q2 into conduction, thereby grounding Vgate.

R9 should be sized to drop the voltage that is not dropped by the LED and limit the LED current to about 10mA.

ZD1 is to protect the LED from accidents.

  • \$\begingroup\$ Thanks Jon. Please let me know where are you supposed to connect Vfet? If it is Q1 drain than D1 and D3 has to be a big one handling min 3A at 55V. \$\endgroup\$ – prasimix Jan 30 '15 at 11:14
  • \$\begingroup\$ Hm, that does not looks promising. Let say that I use Schottky with 0.5V drop on 3A that means additional 3W of dissipation (2 x 0.5 x 3). \$\endgroup\$ – prasimix Jan 31 '15 at 12:57
  • \$\begingroup\$ Oh indeed, since in this mode of operation dissipation on Q1 will be MCU limited to max. 20W. My intention is to use finite heatsink without fan as a noise generator :). One of the limitation is physical space on that heatsink to place two additional let say TO220 schottky or I need to introduce a new smaller one to handle that 3-4W. \$\endgroup\$ – prasimix Jan 31 '15 at 15:54
  • \$\begingroup\$ Correct, but please note that the same circuit is intended to be used with SMPS pre-regulator when full 3A has to flow thru D3 and D1. For the same of simplicity pre-regulator is removed in the picture that accompany this question but it's visible in related question: electronics.stackexchange.com/questions/139361/… \$\endgroup\$ – prasimix Jan 31 '15 at 21:29
  • \$\begingroup\$ Regarding ATTiny: That's a good point, but one of the objective is that PSU should work with and without MCU :) Pre-regulator "bypass" (with 20W dissipation limitation) will be only a feature of the MCU version. \$\endgroup\$ – prasimix Jan 31 '15 at 21:33

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