# What are the rules for combining transistors to form digital circuits?

I just read Harris/Harris - Digital Design and Computer Architecture and in it they described how AND/OR/etc gates are made out of transistors. I read the book for fun (I'm not an EE person, my experience with circuit analysis is minimal) so while I can understand how their circuits work to make the specified gate, I'd like to be able to make my own as an exercise.

In my mind I picture that a NOT gate should be as simple as the input connected to the gate and the output connected to the drain of a P type transistor. It "defaults" to on and when voltage goes up on the gate it cuts off the voltage in the drain. But the book illustrates both a P and N type in series, with the input connected to both gates, and with the output between the drain of the P and the source of the N. So that makes me think that there are some rules about what the gate, source, and drain can be connected to in order to have a working transistor.

So is there any general/simple set of rules for beginners on how to connect transistors into working combinational logic units? I'd like to do this as an activity with someone who knows almost nothing about circuit design (no knowledge of KVL/KCL etc) and as I won't be designing any actual circuits I'd rather avoid studying hard on circuit analysis. Can it be boiled down into a list of rules that I could explain to, say, my grandmother?

• Are you asking why there is a difference in the construction of push-pull outputs in CMOS vs. NMOS gates? – Ignacio Vazquez-Abrams Jan 1 '15 at 4:07
• Depends on your grandmother. And you. :-) . | Look up, in the context of logic circuits and electronics, the terms "Open collector", "totem pole", "push pull", "differential pair", "long tailed pair" then report back. | Also note that "combinatorial" is the correct term (don't blame me :-) ). – Russell McMahon Jan 1 '15 at 6:15

In my mind I picture that a NOT gate should be as simple as the input connected to the gate and the output connected to the drain of a P type transistor. It "defaults" to on and when voltage goes up on the gate it cuts off the voltage in the drain. But the book illustrates both a P and N type in series, with the input connected to both gates, and with the output between the drain of the P and the source of the N. So that makes me think that there are some rules about what the gate, source, and drain can be connected to in order to have a working transistor.

In your mind you aren't making the distinction between LOW and Not Connected.

When your theoretical arrangement is "HIGH" (its "default") state, the output is connected to Vcc. When there is a high enough voltage on the base, the transistor switches off. What is the output connected to then? Nothing at all. It's actually in an indeterminate state, also known as HiZ, or High Impedance. This is one of the three states of Tri-State logic.

The logic "LOW" level doesn't mean "disconnected from Vcc" but instead "connected to GND". You have to have some mechanism for the output to be connected to the ground rail in order for it to sink current and literally be "a low voltage".

What you describe is basically the inverse of the common "open collector" logic gate:

simulate this circuit – Schematic created using CircuitLab

For the logic to make any sense at all an external pull-up resistor to Vcc is required to set the default logic level for the output when the transistor is turned off.

If you were to move the resistor to the inside of the logic gate (the dotted line) then you have what is called RTL - Resistor Transistor Logic.

This is perhaps the easiest logic to understand, since the output is either being linked to ground by the action of the transistors, or is being defaulted to connected to Vcc by the resistor.

However, it's not a particularly efficient system. Far better would be an arrangement whereby you can switch the output between being directly connected to the Vcc or directly connected to GND so you don't drop voltage or waste power over the resistor. Something like a two-way switch:

simulate this circuit

And that's why the totem-pole, or Push Pull arrangement, was born. Two transistors, one connecting the output to Vcc, and one to GND, and only one of them is on at a time. By using a P type to Vcc and an N type to GND you need nothing else to control them since they are naturally the inverse of each other:

simulate this circuit

When D is at a LOW voltage the PNP transistor is turned on, so !Q is connected to Vcc. When D goes to a high enough voltage the PNP turns off and the NPN turns on. Thus, !Q is then connected to GND.

There is usually a "dead" zone between one transistor turning off and the other turning on. This both prevents shoot-through (where both transistors are on at once thus causing a short circuit) and also acts as a noise margin, which you don't get with RTL. For instance, take the following little chart:

Red is where the input voltage is considered to be off, green where it is considered to be on, and yellow is indeterminate. With RTL, if you put in a voltage at or around the switching point, say 0.7V, then what state will it be in? Will it be HIGH or will it be LOW? The slightest noise on the line will make it flip between HIGH and LOW. Not very good really. With TTL the output would switch between LOW and HiZ, and capacitance on the line or other places in that part of the circuit would keep the next stage gate at the same state for a while, effectively destroying the noise.

This is especially good when the transistors are MOSFETs (i.e., CMOS logic) since the gates act just like small capacitors and hold their charge for a while unless specifically charged or discharged by connection to Vcc (through an output's P-channel MOSFET) or to GND (through an output's N-channel MOSFET).

Can it be boiled down into a list of rules that I could explain to, say, my grandmother?

And you. :-) .

The aim of a given logic family is

• To implement a series of mathematical and / or logical abstractions in a real world context

• while adhering to a set of predefined rules which are essentially independent of the logical/mathematical implementation but which affect the practicality and cost effectiveness of the implementation in real world contexts.

That may sound somewhat waffly and vague (and indeed it is) BUT it also is a fair description of what is being achieved.

The transistors themselves are essentially independent of the functions being performed but play a part in allowing the rules to be met.

The rules of how to use transistors in this context boil down to "should produce the desired logic function and meet any level and loading conditions which have been defined for the system being built, at speeds and power levels that meet objectives."

If the output uses an N and P channel part working in unison you can be essentially certain that it allowed some design constraint to be better met than was possible by using only an N or a P channel part plus a resistor.

Look up, in the context of logic circuits and electronics, the terms

• "RTL" (also R.T.L.)

• "DTL", (also D.T.L.)

• "TTL", (also T.T.L.)

• "ECL", (also E.C.L.)

• "MOS",

• "CMOS",

• "Open collector",

• "totem pole",

• "push pull",

• "differential pair",

• "long tailed pair"

then report back.

These should help vastly:

Note that EVERY result is a link to a webpage - usefulness will vary greatly but you can see at a glance what is liable to be of relevance.

A few minutes study of these should make your grandmother's eyes glow. And yours.

RTL, DTL, TTL are in order of historical development and sophistication. RTL has the advantage of low complexity at the cost of rice pudding skin performance levels.

R.T.L. logic

D.T.L. logic

T.T.L. logic

These will be familiar in the context of your original questions:

MOS
NMOS
PMOS
CMOS <- the modern motherload for practical purposes.

Then a useful spin off road that largely ultimately was not mainstream
Schottky aka Schottky TTL

And, of course, ECL & friends - A parallel universe - amongst the very first and still going strong in modern versions for super high performance niche applications.
E.C.L. logic - WARNING - this is a somewhat unusual system. Very fast, power hungry, quirky. Older versions use multiple and unusual power supply levels. Newer ones use fewer supplies and are at the leading edge for super high speed logic.

I wrote the following initially but decided that while it is valuable it is also "somewhat hard going" [tm]. I added the searches above as an easier path.

For interest I Gargoyled on a string of many of the above and obtained one 'hit'.

It was https://archive.org/stream/CircuitDesigns2CollectedCircards/WilliamsCarruthersEvansKinsler-CircuitDesigns2CollectedCircards_djvu.txt
This is a text rendition of the complete 1972 Wireless Worlds Circuit Designs 2 "CIRCARDS" collection. By searching this file for the above keywords (probably with added "."s where relevant you will find many useful snippets.

The original CIRCARDS have diagrams which are absent from this files, alas, but it provides many clues liable to be of value to your grandmother.

eg just this index paragraph gives hints of headier stuff to come:

• C.m.o.s. amplifier/shunt-peaked amplifier/high-gain amplifier/voltage followers/bipolar cascode amplifier/e.c.l. amplifier/f.e.t. cascode amplifiers/amplifiers using t.t.l., r.t.l., d.t.l./d.c. feedback pair/gated video amplifier/high-speed op-amps/c.b. amplifier/up-date circuits.

And this is "pay dirt" for you, although it may not at first be obviously so:

• Simple r.t.l.

The simplest resistor-transistor logic (r.t.l.) gate, which performs the positive logic NOR function, is shown left. A positive voltage applied to any input turns Tr x on, causing Vout to fall from V cc to a value that depends on the base drive. If sufficient base drive is applied, Trx saturates making F ut= FcEsat, representing the logical state. Positive voltages applied to the other inputs increases the degree of saturation and only change Vout by a small amount. If logical voltages (VcEsat) are supplied to all inputs the base- emitter juction of T^ will be only slightly forward biased ( FcEsat » 0. 1 to 0.4V) and Pout ~ + Kcc. For useful logic functions the gate must feed some load, causing an additional current II to flow in Re and hence reducing the logical 1 value of Vout below Fee. The gate is also a negative-logic NAND gate.

Improved r.t.l.

Inclusion of a base bias resistor, Rk in the middle circuit, returned to a negative supply ensures that Tr t is definitely turned off when all inputs are below the input logical 1 threshold and reduces the transistors turn-off time. Speed-up capacitors can be placed in parallel with each input i?B to produce resistor-capacitor- transistor logic. However, if all inputs are at logical 1 voltages and one of them rapidly switches to the 0-state, its speed-up capacitor couples the negative- going transition to the base- emitter junction of Tr x which can cause the transistor to temporarily switch off. For this reason r.t.l. gates are normally only used at fairly low switching speeds.

A clamping diode D b shown right, can be connected to a supply + Vv> < + Kcc to make the logical 1 output voltage less dependent on the load current, provided that the drop across Re does not cause D,. to become reverse-biased.

Note that "combinatorial" and not combinational is the correct term in this context (don't blame me :-) )

Russell gave a great overview of various logic families, and you should explore the many references in his answer.

In terms of actually building some circuits and experimenting with them, I suggest using DTL (diode transistor logic), which along with RTL (resistor transistor logic), were two of the early logic families used successfully used in several large projects in the 1960's, like the Apollo guidance computer (RTL), IBM 360 (DTL), and Minuteman II guidance computer (DTL).

DTL has some performance improvements over RTL (such as greater fan-in). On the other hand, it is simpler than TTL (transistor transistor logic) circuits for the same function. (Logic designers quickly switched over to using TTL for integrated circuits because its easy to implement transistors on an IC.) All of these (RTL, DTL, TTL) used BJT's (Bipolar Junction Transistors). They were later replaced by CMOS using FET's (Field Effect Transistors), which use much less power.

The two building blocks of logic circuits are the NAND gate and the NOR gate. All other logic functions can be made out of either of these two. (For example, the Apollo guidance computer used 5600 3-input NOR gates and nothing else to implement all of its logic.)

The truth tables for the NAND and NOR gates aare:

      NAND                      NOR

A  B     Out              A  B    Out
------------              -----------

0  0      1               0  0     1
0  1      1               0  1     0
1  0      1               1  0     0
1  1      0               1  1     0


Here is a simplified NAND gate:

If either or both inputs are a logic 0, i.e. ground, one or both diodes will conduct, so the base of the transistor will be at the V$_{f}$ of the diodes, or about 0.7v. This will not be enough to turn on the transistor (well, very close to V$_{BE}$, see below) so the output of the transistor will be near +5, or a logic 1, as shown in the truth table above.

If both A and B are logic 1 (+5), then neither diode conducts, and 5v is applied to the base of the transistor, turning it on. This then puts a ground (actually V$_{CE}$, or about 0.2v) on the output, representing a logic 0.

In practice, one or more diodes are placed between the input diodes and the base of the transistor, to set a higher threshold to insure the transistor doesn't turn on when either input is low. In addition, a resistor can be placed between the base and ground, so the transistor turns off faster when the base current is removed.

Here are some DTL circuits for implementing NAND, NOR, AND, OR, and NOT:

You can use the ubiquitous IN4148 for all the diodes, and any general purpose NPN transistor such as the 2N3904.

Note that the AND is just a NAND with an inverter tacked on, and the same for the NOR and OR.

These circuits are adapted from this document, which includes an exhaustive circuit analysis of the NAND gate circuit.

All of the circuits are designed so the outputs of one gate feed into the inputs of another.

Probably the most basic rule is that each output should be connected to either power or ground at all times, but never both. There are a couple exceptions to this, but it's a good starting point for CMOS logic. You can't leave an output floating (as in your suggestion) because CMOS inputs don't have a path to power or ground, so their values would not be predictable.