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I have been reading up why a flash ADC does not (theoretically) need a sample and hold circuit. I have learned that this is because the comparators have an inherent sample and hold property, but I can not see why this is so. So please could you explain why a (op-amp) comparator has an inherent sample and hold property.

Some sources where this property is mentioned:

  1. http://www.ijsrd.com/articles/IJSRDV2I3184.pdf
  2. http://www.analog.com/static/imported-files/tutorials/MT-020.pdf
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  • \$\begingroup\$ I don't understand why S+H would matter at all. Either the voltage is greater than the reference, or it is not. \$\endgroup\$ – Ignacio Vazquez-Abrams Jan 1 '15 at 20:11
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Whoever told you that was mistaken. The papers you cite are talking about "latched comparators" that are specifically designed to have internal storage of their state. These are specifically designed to support ADCs.

The reason most ADCs require sample-and-hold circuits is that they require a certain amount of time to make a conversion, and the analog sample must remain stable for that period of time, or else the output bits will be inconsistent.

Flash ADCs (at least theoretically) take zero time to make a converstion, or put another way, they are converting continuously. If all of the comparators had precisely the same delay, and you didn't have to worry about metastability, you could capture their outputs at any time and directly convert the results to a binary number.

In practice, you do need to worry about metastability, since the comparator outputs can change at any time, and the digital logic that follows has a clock associated with it. Also, the comparators do not all have the same delay. So, either a short sample-and-hold circuit is used ahead of the comparators, or else two-stage synchronization along with an error-tolerant form of thermometer-to-binary conversion logic is used at their outputs.

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In general, comparators (at least the ones you buy to mess around with) do not have a latch capability. Those that do form a limited subset of comparators, and are specifically called "latching comparators".

"Regular"comparators are those like the LM311 or LM339, and are the most commonly used sort.

"Latching (or Latched)" comparators such as the Linear Technology LT1016 are always high-speed devices.

You'll note that the first article you linked to found it appropriate to discuss just how they got the latching function and how it works. This should have been a tipoff that there was something unusual about it.

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