I have a top modul VHDL source file, which has a few instances of lower-level modules (VHDL) and signals which connects these lower-level modules. How can I generate a schematic for this? I mean, I would like to see the top module, inside it, the lower-level modules and the signals. (xilinx ise design suite 14.7)
Xilinx ISE 14.7: Design tab -> Synthesize - XST (expand node) -> View RTL Schematic.
Alternative: menu Tools -> Schematic Viewer -> RTL...
RTL Schematic (Register Transfer Logic) is the generic, hierarchical schematic in terms of combinational logic and flip-flops. The other choice is Technology Schematic, which shows how the logic maps to device-specific low-level elements such as slices and IOB.