simulate this circuit – Schematic created using CircuitLab

Here is the low pass I have used. I used the 347 op amp just because it was cheap from a local surplus house. I will get discrete values off a board if needed.


I have used this circuit to generate sine waves that are one sixth of the clock frequency. With a low pass filter on output it generates a really clean sine wave. I am not real familiar with the stack exchange circuit editor, so I was not able to get an HC74 or 4018, so I added an inverter to show the last stage /Q going to the first stage D input. I no longer remember where I found the original circuit, but I do have some notes that read as follows:

7 stage 14x clock resistors 22.1k 40.2k 49.9k 49.9k 40.2k 22.1k

8 stage 16x clock resistors 22.1k 41.2k 53.6k 57.6k 53.6k 41.2k 22.1k

There are a few specific things I want to be able to understand.

1 How does a circuit designer take an arbitrary n-stage walking ring divider circuit and calculate the weighting resistor values that make the sine approximation to feed the low pass filter? I tried using an Excel spreadsheet sine function, but I was never able to get close to resistor values that I know work.

2 What is the algorithm to determine the signal strength of the harmonics generated by the circuit? So far, my lo pass filters have been trial and error to get good results. What I have read so far suggests filters are designed knowing (or at least planning for) the worst case input signal.

3 Will this approach work for TTL as readily as CMOS?

I am certain that there are several other approaches to generating multiple clean sines from digital logic; this particular one also provides useful osc/n signals that make it appealing to me.

If the scope of the question is too large for this forum; I would still be pleased with a pointer to a reference book to purchase and read.


  • \$\begingroup\$ @Steverino:Your active filter is NOT a lowpass - it is a highpass! \$\endgroup\$
    – LvW
    Commented Jan 3, 2015 at 9:17
  • \$\begingroup\$ @LvW I fixed the filter. I put the wrong one in the editor at first. \$\endgroup\$
    – steverino
    Commented Jan 3, 2015 at 10:23

2 Answers 2


The waveform generated by your circuit is special, because unlike a plain square wave, it contains no 3rd harmonic at all, nor any multiples of the 3rd harmonic (9th, 15th, 21st, etc.). The waveform contains only the fundamental, and the 5th, 7th, 11th, etc. harmonics:


This is a huge advantage for synthesizing sinewaves, since the filter only needs to suppress those higher-order harmonics.

In order to understand this, it's helpful to view it in terms of the phasor diagrams for each of the harmonics:

waveform showing components

If we set the 0° point of the waveform at the center of the rising zero crossing, as shown below, the symmetry of the phasor diagram becomes more obvious.

phasor diagram for 3-stage counter

Relative to the 0° point, the A waveform's fundamental crosses zero 30° earlier (–30°) and the B waveform's fundamental does so 30° later (+30°). The sum of these two components aligns with the 0° axis, and has a magnitude equal to 1.732× the amplitude of A or B alone.

The third harmonics have phase shifts that are 3× that of the fundamentals, putting them at –90° and +90° on the phasor diagram. Clearly, they directly cancel each other, leaving none of that component to appear in the output.

The fifth harmonics have phase shifts of 5× the fundamentals, so they add in the same proportion as the fundamental, resulting in no net change in amplitude relative to the original squarewave alone.

So, if you have four flip-flops and three resistors, how would you calculate the resistor values to get the best approximation to a sinewave?

Start by drawing the phasor diagram for this case. We now have three waveforms, A, B and C, separated by 45° as shown below.

waveforms for 4-stage counter

The fundamentals have the relationship shown below. The B signal is aligned with the 0° axis, but the A and C waveforms are at –45° and +45°, respectively. The net sum will be B + 1.414×(A or C).

phasor diagram for 4-stage counter

The third harmonics a A and C have 3× the phase shift of the fundamentals, placing them at –135° and +135°, respectively, as shown below. It becomes clear that the sum of A and C can be used to cancel B if the amplitudes of A and C are equal to each other, and equal to \$1/\sqrt{2} = 0.707\$ the amplitude of B.

Going back to the fundamental diagram, this means that the net total of that component will be 2× the level of B alone.

phasor diagram for 3rd harmonic of 4-stage counter

Similarly, the fifth harmonics a A and C have 5× the phase shift of the fundamentals, placing them at –225° and +225°, respectively, as shown below. Although they have switched positions, the A and C components will cancel the B component exactly as in the third-harmonic case shown above.

phasor diagram for 5th harmonic of 4-stage counter

This technique can be generalized to even more stages. Each added stage cancels another set of harmonics if the resistor values are set correctly.

By cancelling low-order harmonics in this way, only the higher-order ones need to be filtered out, making it easy to synthesize high-quality sinewaves with a simple combination of digital and analog components.

Note that there's a limit on how far it makes sense to take this. For example, if you use 1% resistors, the cancellation of harmonics is not going to be perfect. The errors will accumulate at a rate roughly proportional to the square root of the number of stages, which means that for an N-stage synthesizer, the overall error will be \$\sqrt{N}\cdot 1\%\$.

There would be no point to adding another stage if the level of the harmonic to be cancelled would be less than this error amplitude. Since the harmonic amplitudes are proportional to 1/(2N–1), we simply need to find the value of N for which 1/(2N–1) < \$0.01\cdot \sqrt{N}\$.

It doesn't take much trial-and-error to discover that this happens at about 13 or 14 stages.

  • \$\begingroup\$ Wouldn't it be reasonable to push this to N=20 if using Vishay metal foil resistors @.1 or .05%? The ease of getting multiple digital sines that are precisely phased would seem to make this attractive for 3ph inverters for example. That would make 400hz doable with a cheap 32 khz crystal. \$\endgroup\$
    – steverino
    Commented Jan 4, 2015 at 20:59
  • \$\begingroup\$ @steverino: Maybe, but I suspect that it might be well beyond the "knee" on the diminishing-returns curve. You'd be better off putting the effort into a better filter. Also, there are much better ways to generate high-quality sine waves using DSP techniques on modern chips. \$\endgroup\$
    – Dave Tweed
    Commented Jan 4, 2015 at 21:11
  • \$\begingroup\$ @steverino: Also, as I've pointed out in another question, if you want to make high-power sinewaves, starting with a low-power sinewave is not usually the best approach. It's much more straightforward to synthesize the gate-drive signals for the class-D power stage directly. \$\endgroup\$
    – Dave Tweed
    Commented Jan 4, 2015 at 21:18

1) That kind of counter is called a Johnson counter, and your circuit is a digital to analog converter (DAC) where the outputs of the registers are totem poles which can switch between Vcc and GND.

In order to determine the values of the resistors, first determine the resolution of the ADC, in degrees, by dividing the number of stages into 180°.

enter image description here

Next, since you want to synthesize an 8-step sine wave with 45° between steps, what you'll want to do is look up the sines of those angles:

    PHI    SIN
     0      0  
    45     0.71
    90      1
   135     0.71
   180      0
   225    -0.71
   270     -1 
   315    -0.71
   360      0

Then, since you (probably) want the output of the DAC to vary between zero volts and some positive voltage, normalize the table so that the counter's outputs at 0000 (270°) equal zero and at 1111 (90°) they equal 1. You can scale the range linearly with a single multiplier to cover whatever voltage span you want later.

    PHI    SINN
     0     0.5  
    45     0.824
    90     1
   135     0.824
   180     0.5
   225     0.176
   270     0 
   315     0.176
   360     0.5

Now, the resistors:

From the following, you can see that (except for 0000 and 1111) the resistors are arranged as voltage dividers, with their output voltages dependent on their input voltages - which will be either Vcc or 0V, depending on whether the counter's Qs are 1 or 0 - and the various series and parallel resistor combinations that will effect.

enter image description here

Interestingly, from the counter schematic, if R1 = R4 and R2 = R3, then when the counter is at either 0011 or 1100, DACOUT will always be equal to Vcc/2, and from the symmetry of the count, it appears that with R2 and R3 equal and fixed, a pair of equal valued resistances can be selected for R1 and R4 which will satisfy the rest of the sine table.

Referring to 1110, above, the circuit is equivalent to a two-resistor divider:

enter image description here

Arbitrarily selecting R2 at 100k and plugging in the normalized voltage values for a 45° step down from 1 volt gives us:

enter image description here

R1 comprises three resistors in parallel with a total resistance of 21.5k, and since one of them must be 100k, we have:

enter image description here

But, R3 comprises two equal valued resistors in parallel, so the value of either must be twice the value of the pair. Finally, with our resistor array keyed to the counter schematic, we arrive at:

enter image description here

If you'd like to play with the circuit, the LTspice files are here; just load them all into a single folder and run the .asc file with LTspice.

2) Re. your question on harmonics, take an FFT of the DACOUT waveform and you'll see them nicely displayed. Of particular interest, notice that the clock and its harmonics are way down in the noise, but there are sidebands and the IF is there (your switched sinewave), so the thing is acting like a balanced mixer.

3) Re. your question about TTL, it won't work as well as CMOS because it doesn't swing rail-to-rail like CMOS does.

BTW, Here's the LTspice plot of the DAC CLEAR, CLK, and DACOUT:

enter image description here

the DAC:

enter image description here

and the FFT of DACOUT:

enter image description here


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