Here is the low pass I have used. I used the 347 op amp just because it was cheap from a local surplus house. I will get discrete values off a board if needed.
I have used this circuit to generate sine waves that are one sixth of the clock frequency. With a low pass filter on output it generates a really clean sine wave. I am not real familiar with the stack exchange circuit editor, so I was not able to get an HC74 or 4018, so I added an inverter to show the last stage /Q going to the first stage D input. I no longer remember where I found the original circuit, but I do have some notes that read as follows:
7 stage 14x clock resistors 22.1k 40.2k 49.9k 49.9k 40.2k 22.1k
8 stage 16x clock resistors 22.1k 41.2k 53.6k 57.6k 53.6k 41.2k 22.1k
There are a few specific things I want to be able to understand.
1 How does a circuit designer take an arbitrary n-stage walking ring divider circuit and calculate the weighting resistor values that make the sine approximation to feed the low pass filter? I tried using an Excel spreadsheet sine function, but I was never able to get close to resistor values that I know work.
2 What is the algorithm to determine the signal strength of the harmonics generated by the circuit? So far, my lo pass filters have been trial and error to get good results. What I have read so far suggests filters are designed knowing (or at least planning for) the worst case input signal.
3 Will this approach work for TTL as readily as CMOS?
I am certain that there are several other approaches to generating multiple clean sines from digital logic; this particular one also provides useful osc/n signals that make it appealing to me.
If the scope of the question is too large for this forum; I would still be pleased with a pointer to a reference book to purchase and read.