# Anticipating processing delay in embedded systems

Background:

I have been working with the STM32F3 discovery board and I am trying to implement some signal processing algorithms from the ground up. My problem is shown below in the graph. The more taps I add to an FIR filter, the longer the delay between the input signal and the DAC output signal. For the audio signals I am using, a delay over 40 us will cause distortion that can be heard, limiting my filtering capabilities. It also makes it difficult to design the filter because the sampling rate is limited by the computation time (the next input cannot be processed until the previous is sent to the output).

Questions:

Are there hardware or software structures that I should be making use of that improve performance?

If I cannot improve performance, should I design my filter with a sampling rate that takes into account the number of operations I need to perform between samples and the operation time from the datasheet?

I haven't tried the CMSIS libraries since I wanted to get a better feel for the actual algorithms but would these libraries improve performance?

Code Snippets: (Generalized for IIR Filters)

while (1)
{
DAC_SetChannel2Data(DAC_Align_12b_R, FilteredValue);
}
uint16_t filter(__IO uint16_t nValue)
{

for(i=(Taps-1);i>0;i--)
{
x[i]=x[i-1];
y[i]=y[i-1];
}
x[0]=nValue;
y[0]=0;
for(j=1;j<Taps;j++)
{
y[0]= y[0]+(b[j]*x[j])-(a[j]*y[j]);
}
y[0]=y[0]+(b[0]*x[0]);
return y[0]+1024;
}


ADC_RegularChannelConfig(ADC1, ADC_Channel_7, 1, ADC_SampleTime_1Cycles5);


DAC Timing Setup

TIM_TimeBaseStructure.TIM_Period = 2-1 ;
TIM_TimeBaseStructure.TIM_Prescaler = 1-1;
TIM_TimeBaseStructure.TIM_ClockDivision = 1-1;


Thanks for your time and I would appreciate any guidance!

• Your requirement of less than 40us delay is rather suspect for "audio", and going to be unachievable (theory, regardless of implementation) for all but the most trivial filtering. – Chris Stratton Jan 4 '15 at 4:30
• I set 40us as the threshold for a sampling frequency of 25KHz which is the upper range of human hearing. Ideally I would like more than one sample point per period here as well for signal reconstruction. I thought that the STM32F3 that runs off a 72MHz clock would be up to the task. If this is unachievable, how would one go about implementing a digital filter for high frequency signals? – Andrew Jan 4 '15 at 19:45
• The problem is theoretical: regardless of compute speed any useful discrete time filter has a delay of multiple sample periods as delayed versions of the signal appear in the filter expression (explicitly for an FIR, implicitly and usually also explicitly for an IIR). Only if you can comparably delay whatever other path you measure delay relative to can you achieve less. – Chris Stratton Jan 4 '15 at 19:48
• What I am saying is that while your computation has to keep up with your data rate, the bulk of your delay (multiple sample periods) comes from waiting for the necessary input samples to calculate an output (plus any pipelining you might use). – Chris Stratton Jan 4 '15 at 20:17