In an Intel guideline for their 82579 Gigabit Ethernet controller I've read (p. 18) that a side effect of using serpentine traces on the MDI (which carries the actual Ethernet signals) leads to decreased ESD immunity. I'm fairly familiar with the other ills of serpentine traces (cross-talk leading to ladder-like waveforms, increased EMI etc.), but I'm scratching my head trying to figure out how serpentines might affect ESD immunity.
On page 18 of the referenced document, it mentions that long serpentine traces can contribute to radiated EMI and decreased ESD immunity.
As for the radiated EMI portion, this may be due to the fact that "long serpentine traces" can unbalance the circuit and potentially cause an emissions problem when used with unshielded RJ-45 cables. This is really a layout consideration.
As for your primary question on ESD immunity, I personally don't think think the person that wrote the excerpt on page 18 knows what they are talking about. More than likely what the author meant was "RF immunity" instead of "ESD immunity", which is a big difference.
This makes sense since that if there is a design guideline that could cause emissions problems that due to reciprocity there also could be immunity issues as well.
Just so I don't leave this hanging with a somewhat wrong answer marked as accepted (before I take a break from this site): what I think Intel means is that ESD can produce significant EM fields, even if the ESD is shorted by a TVS/ESD diode, and those EM fields can get picked up by nearby serpentine traces, thus negating much of the TVS diode's benefit. There are some interesting simulations of ESD-generated EM fields in Joffe and Lock's Grounds for Grounding book (pp. 878-879) with multiple ESD-shorting implementations; it's upon seeing those that I figured out what's the likely mechanism for this. Basically EMI susceptibility implies ESD susceptibility.
Scanning the surface populated PCBs for susceptibility to ESD-induced EMI is a fairly active area of research. There are various commercial systems out there and a scanning standard is supposedly being baked by ESDA. I found a 2008 overview paper on the topic co-authored by several industry researchers, including some from Intel, doi:10.1109/TEMC.2008.921059; there's a free copy of that on the company website of one of the co-authors. I also found a 2014 EDN article "Embedded scanning: The next step in ESD detection" on the (purported) 4th generation method of doing the same scanning better by embedding some measurement circuitry right in the ICs. One can only guess how much adoption this latter technique is going to have in the future, but the article is also an overview of the more widespread scanning methods.