In this link is a description of the Altera DE1-SoC kit, and the bottom of the page shows the diagram of the SoC-FPGA chip. It shows some peripherals are connected to the FPGA and other are connected to the HPS. The question is, Does that implies that peripherals connected to the HPS I can't use them with the FPGA and vice versa ?
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\$\begingroup\$ Maybe you should be more precise: Do you mean if each side can access peripherals on the other side in a common way (through CPU or memory) or do you mean for example if the FPGA part has full pin access. \$\endgroup\$– PaebbelsCommented Jan 6, 2015 at 5:22
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\$\begingroup\$ If each side can access the other side's peripherals. The access mechanism is another thing but first if it can or not. \$\endgroup\$– 3bdallaCommented Jan 6, 2015 at 6:47
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\$\begingroup\$ Ok, I misunderstood your question. I thought you asked for a direct and unrestricted access to the peripherals of the other side. Of cause you can access certain periphery through direct memory access (DMA), if the devices are mapped to memory as described by @apalopohapa. Otherwise a SoC with an embedded FPGA part would not make any sense :) \$\endgroup\$– PaebbelsCommented Jan 6, 2015 at 11:56
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\$\begingroup\$ Accessing peripherals through the HPS-FPGA bridge offers no direct access to pins. It's not a low latency connection and in some cases it's not even real-time. For example, if you want to use the UART port in the FPGA part, you have to implement a complete bus master instead of an simple UART controller. On the other side, if you want to use VGA in your CPU part, you have to implement a VGA controller with either an self defined register/memory interface and your own drivers, or you reimplement/reuse a well known VGA controller which provides drivers for your operating system/software. \$\endgroup\$– PaebbelsCommented Jan 6, 2015 at 12:07
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\$\begingroup\$ This topic seems more complicated than I thought, It needs more study and work. Anyway thanks for the tips guys :) \$\endgroup\$– 3bdallaCommented Jan 6, 2015 at 21:20
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2 Answers
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Yes you can. This is simply an FPGA with a hardware ARM core instead of a soft ARM core (as the one you might want to instantiate in a regular FPGA). The hardware ARM core is connected internally to the FPGA logic through a high bandwidth interconnect Backbone. Here you can read a more detailed explanation: http://www.altera.com/devices/fpga/cyclone-v-fpgas/hard-processor-system/cyv-soc-hps.html
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Yes, you can. Here's an excerpt of the Cyclone V HPS manual:
HPS-FPGA Interfaces
The HPS-FPGA interfaces provide a variety of communication channels between the HPS and the FPGA fabric. The HPS-FPGA interfaces include:
• FPGA-to-HPS bridge—a high-performance bus with a configurable data width of 32, 64, and 128 bits, allowing the FPGA fabric to master transactions to the slaves in the HPS. This interface allows the FPGA fabric to have full visibility into the HPS address space. This interface also provides access to the coherent memory interface.
• HPS-to-FPGA bridge—a high-performance interface with a configurable data width of 32, 64, and 128 bits, allowing the HPS to master transactions to slaves in the FPGA fabric.
answered Jan 5, 2015 at 19:36