One way of scaling a chip is to scale all length, width, and thickness (in particular, the oxide thickness) proportionally to some scale factor S.
The result (neglecting fringing effects):
The transistor channel resistance stays the same (no improvement).
The transistor gate capacitance scales proportionally to S (a little improvement).
The wiring capacitance scales proportionally to S^2 (a lot of improvement).
The wiring resistance scales proportionally to 1/s (a little worse).
Since typically the channel resistance and gate capacitance dominate, let's assume that that the every capacitance scales to S and every resistance is unchanged -- a pretty good approximation for most chips (in fact, a bit pessimistic).
The time to switch a node is proportional to RC, so since we kept R constant and improved C, we could run the chip faster.
As Bitrex said, P = C(V^2)f.
Assuming we run the new, shrunken chip at exactly the same clock rate and voltage as the original chip, the power dissipated by the chip also scales with S.
(Often we are forced to reduce the voltage V because we used thinner oxide that can't handle the original voltage; that reduces power even more -- let's be pessimistic and neglect this possibility).
If Apple actually does shrink the chip by a factor of 22/45 -- roughly half -- then power used by that chip also shrinks by the same amount.
If we assume that chip uses nearly all the power consumed by the iPad -- i.e., if the power used in the data store, the screen, the buttons, the speaker, etc. is negligible in comparison (this may be a bit optimistic),
then an iPad with the shrunk chip could run roughly twice as long as the original chip before draining the batteries.
Or alternatively, an iPad with the shrunk chip could run the same amount of time as the original chip with batteries that weigh roughly half as much.