So to the background of my question, there has been a rumor around that Apple might use Intel's fab to manufacture their A4 or A5 chips as they no longer source them from Samsung. The article then goes on to state that Apple might then benefit from Intel's knowledge of a 22nm process and that would mean some power savings for them, giving them a quite a large amount of power savings over their current 45 nm process.

So my questions is in two parts; How much power saving does a die shrink offer all things being equal and Is there a mathematical formula for this for calculating the power consumption as a function of process size?

The last thing I would like to add, that is more conjecture then anything else, because we just don't know; that is, until Intel releases a product using their 3D transistor platform; how much benefit do 3D transistors add to the overall power efficacy of the chip?

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    \$\begingroup\$ Split the 3d part into a separate question. \$\endgroup\$ – Brian Carlton Aug 9 '11 at 0:39
  • \$\begingroup\$ Wow, this question didn't age well at all. \$\endgroup\$ – Mark Tomlin Mar 8 at 3:19

I can help to address the first part of your question. As an abstraction of a single switching device inside a processor, imagine a MOSFET connected to ground with a load resistor to the power supply (in a real CMOS part there wouldn't be a load resistor, but another transistor, but this distinction is not important for the analysis). Connected from the junction of the resistor and the transistor is a capacitor, representing all the input capacitances of the transistor that the transistor under discussion is driving. When the first transistor switches off, this capacitance will be charged up through the load resistor. When the first transistor switches back on, the charge stored on the capacitor will be discharged through the first transistor.

It can be shown that when a capacitor is charged through a load resistor, 1/2 of the energy used in charging the capacitor is lost in the resistor, for a total energy dissipation of \$\frac{1}{2}C{V_s}^2\$, where \$V_s\$ is the supply voltage. When the switch then turns on, assuming the resistance of the switch is much less than the load resistance, that same energy will be dissipated in the switch, for a total energy of \$C{V_s}^2\$. Dividing this by the switching period gives you the dynamic power dissipation of the switch/capacitance combo, \$C{V_s}^2f\$. Shrinking the die reduces the junction capacitances of the MOSFETS, so if you know the supply voltage, switching frequency, number of transistors and the approximate junction capacitances of a certain process, you could calculate a ballpark figure of what kind of power savings a process shrink entails, all other things being equal.

  • \$\begingroup\$ So from the details of just it's clock speed, the number of transistors, voltage, and watts and size could you give me an example equastion for 1GHz, 47 Million, 45 nm, 1 Volt, and 5 Watts could you use these numbers to calculate it's power usage in say, watt hours? \$\endgroup\$ – Mark Tomlin May 29 '11 at 3:40
  • \$\begingroup\$ @Mark: It doesn't work that way in general (not all the transistors are in use at the same frequency). Also the question in your comment makes no sense. If you want energy use in watt-hours you need to know time. If you want power use in watts, you've already stated 5 watts so what's the question? \$\endgroup\$ – Jason S May 29 '11 at 11:18

One way of scaling a chip is to scale all length, width, and thickness (in particular, the oxide thickness) proportionally to some scale factor S.

The result (neglecting fringing effects):

The transistor channel resistance stays the same (no improvement). The transistor gate capacitance scales proportionally to S (a little improvement). The wiring capacitance scales proportionally to S^2 (a lot of improvement). The wiring resistance scales proportionally to 1/s (a little worse).

Since typically the channel resistance and gate capacitance dominate, let's assume that that the every capacitance scales to S and every resistance is unchanged -- a pretty good approximation for most chips (in fact, a bit pessimistic).

The time to switch a node is proportional to RC, so since we kept R constant and improved C, we could run the chip faster.

As Bitrex said, P = C(V^2)f.

Assuming we run the new, shrunken chip at exactly the same clock rate and voltage as the original chip, the power dissipated by the chip also scales with S. (Often we are forced to reduce the voltage V because we used thinner oxide that can't handle the original voltage; that reduces power even more -- let's be pessimistic and neglect this possibility).

If Apple actually does shrink the chip by a factor of 22/45 -- roughly half -- then power used by that chip also shrinks by the same amount. If we assume that chip uses nearly all the power consumed by the iPad -- i.e., if the power used in the data store, the screen, the buttons, the speaker, etc. is negligible in comparison (this may be a bit optimistic), then an iPad with the shrunk chip could run roughly twice as long as the original chip before draining the batteries. Or alternatively, an iPad with the shrunk chip could run the same amount of time as the original chip with batteries that weigh roughly half as much.


Answer: The reason Apple goes to Intel, is becasue Intel decided to make ARM to attract Apple.

Technical details: 22 nm by Intel introduces finFET. Intel is possibly the only company at the moment which has commercial volumes of finFET bases devices available from fabs.

The point about gate capacitance (above) and RC cost is valid, but it is not the major effect at low nm sizes. The dominating factor is gate leakage in pA range. Dielectrics thicknesses are approaching few atoms (about 5 atoms of high-K or other dielectric material). The leakage is caused by tonnel effects, thermal electron emission and more.


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