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The way I understand it, the input value (D) of a D type flip-flop appears immediately on the output (Q) of a D type flip when triggered by a positive clock edge. If this is the case, then how can the value before the clock edge be used as an input to another clocked flip-flop? According to this model, there's no particular value at all right at the edge of the clock.

Of course, flip-flops do work so it's my model of understanding which is wrong. So can anyone elaborate this a bit more?

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If you scrutinize the data sheet for a real D-FF carefully, you will see an item called 'setup time'. In actuality, the FF doesn't grab the value at the exact time of the clock edge; the data has to be stable for the last 20 ns or so before the clock rises, and that's the value that gets transferred. Also, the value at the output takes a few ns to settle down to the (possibly) changed value. So if you daisy chain a string of D-FF's together, Q from one into the D of the next, everything works because during the critical time for each stage's D input, the Q's are stable; the Q's only change very shortly after the active clock edge.

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    \$\begingroup\$ The key specification isn't setup time, but hold time; see my answer below. \$\endgroup\$ – supercat May 29 '11 at 22:37
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The setup and hold times of a D flip flop together specify an interval during which any change to the data input may cause arbitrary behavior. If a flip-flop has a 7ns setup time and a 5ns hold time, that means that if a clock edge happens within 7ns after an input change, or the input changes within 5ns after a clock edge, the behavior of the latch is not guaranteed. It is possible for either the setup or hold time (but not both) to be negative; the magnitude of the other time bust be greater than that of the negative time. If a latch had, e.g. a specified setup time of 11ns and a hold time of -4ns, that would mean that the behavior of the latch would be guaranteed unless the clock input changed between 11 and 4ns after a change to the data input.

Note that while setup and hold times are usually specified as maxima, they are in reality absolute worst-case values since the manufacturer makes no guarantee as to what would happen were they violated. For example, suppose chip X has 10ns setup and hold times, while chip Y has 1ns setup and hold times, and that both chips are fed a data signal which changes 7ns before a clock edge. Chip Y would be required to latch the data signal correctly; chip X could do just about anything--including latching the data signal correctly--and be deemed to meet spec. It would be pointless for a manufacturer to specify that a minimum setup time (unless the intention was really to specify that the maximum hold time was negative, in which case that's what the spec should say).

Almost any process which is used to make flip flops will effectively guarantee that the shortest propagation time for any of the flip flops on the chip will be longer than the longest setup time for any similarly-specified flip flops. In most cases, this guarantee effectively seems to extend to other chips in the same manufacturing lot, but it's unclear how far it really extends. In many cases, manufacturers specify that a chip's hold time will be no longer than some amount, and that the propagation time will be no longer than a certain amount, but unless the hold time is zero or negative or a minimum propagation time is specified and it's longer than the required hold time, I don't think the data sheets actually specify correct operation for cascading latches. Certainly it's possible to have trouble when feeding the data output of a very fast chip into the data input of a slow chip with a long hold time.

One approach that's used with some protocols like SPI, and it's an approach I'd like to see used more, is to have the output stage of each latch change on the opposite clock edge from the input. I'm not sure why this approach isn't used more; while there are times when it would be unnecessary and wasteful (if one knows that the propagation time of the circuitry between two latches would be sufficient to satisfy the hold time of the downstream latch, having the output of the upstream latch change on the same clock edge as downstream latch is sampled would allow for higher clock speeds), it also makes it possible to guarantee the correctness of many circuits involving mixed logic families--something which may otherwise be difficult.

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  • \$\begingroup\$ The data changing on the negative clock edge is actually how my teacher said it behaved but it seems that this is not very common and that was what made me confused. But now it certainly makes sense :) \$\endgroup\$ – Emil Eriksson May 30 '11 at 14:20
  • \$\begingroup\$ @Emil Eriksson: I'm surprised that there aren't more "jellybean" chips (74xx and 40xx, etc.) which sample on one edge and output on the other. For designs within a chip, there's generally no problem ensuring that clocks get distributed so as to satisfy setup/hold requirements, and latches which feed each other can be assumed to be part of the same process lot (since they are of course on the same die). When going between chips, it's harder to ensure that setup/hold times are met. I'm really curious why the split clock behavior isn't more common... \$\endgroup\$ – supercat May 30 '11 at 15:40
  • \$\begingroup\$ @Emil Eriksson: ...especially since it's actually easier to implement in silicon than a chip where the output changes on the same edge as the input. \$\endgroup\$ – supercat May 30 '11 at 15:41
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Propagation delay.

Just like an inverter or in fact any other logic gate the output does not change immediately with the input.

For example, for the 74F74, a dual D-type flip flop with dedicated S and R inputs, there are two propagation delays specified: "Propagation delay CPn to Qn or Qn#" and "Propagation delay "SDn#, RDn# to Qn or Qn#". Both take less than 11 ns worst case.

Now, it is fun to consider what would happen if logic gates had zero propagation delay. Let's take the D-type, set up as a binary counter. Assume Q = 0, Q# = 1. A rising edge occurs on the clock pin. Immediately (in zero time), Q# is transferred to Q. Now, with all logic gates, the rising edge detection logic can output a rising edge for some time, say a few ns. So for these few ns (required to be shorter than propagation delay for stability, but in this case greater) we get oscillations. Q# becomes 0, and gets transferred to Q. Then Q# becomes 1, and gets transferred to Q... and so on. The output is known as indeterminate.

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It doesn't means that the D-Flipflop giving the output immediately
it evaluates the Input signal as per its connections and gives the output.
Just i will remind you the truth table of JK-flipflop:

enter image description here

Here in D-Flipflop the Circuit diagram is like this: enter image description here

and it truth table is :
enter image description here

here use these inputs to the this circuit by considering the previous state then
you will get the output as same as that as the input you given to the D-flip flop
thats it but it doesn't means it won't use the previous state.

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