The setup and hold times of a D flip flop together specify an interval during which any change to the data input may cause arbitrary behavior. If a flip-flop has a 7ns setup time and a 5ns hold time, that means that if a clock edge happens within 7ns after an input change, or the input changes within 5ns after a clock edge, the behavior of the latch is not guaranteed. It is possible for either the setup or hold time (but not both) to be negative; the magnitude of the other time bust be greater than that of the negative time. If a latch had, e.g. a specified setup time of 11ns and a hold time of -4ns, that would mean that the behavior of the latch would be guaranteed unless the clock input changed between 11 and 4ns after a change to the data input.
Note that while setup and hold times are usually specified as maxima, they are in reality absolute worst-case values since the manufacturer makes no guarantee as to what would happen were they violated. For example, suppose chip X has 10ns setup and hold times, while chip Y has 1ns setup and hold times, and that both chips are fed a data signal which changes 7ns before a clock edge. Chip Y would be required to latch the data signal correctly; chip X could do just about anything--including latching the data signal correctly--and be deemed to meet spec. It would be pointless for a manufacturer to specify that a minimum setup time (unless the intention was really to specify that the maximum hold time was negative, in which case that's what the spec should say).
Almost any process which is used to make flip flops will effectively guarantee that the shortest propagation time for any of the flip flops on the chip will be longer than the longest setup time for any similarly-specified flip flops. In most cases, this guarantee effectively seems to extend to other chips in the same manufacturing lot, but it's unclear how far it really extends. In many cases, manufacturers specify that a chip's hold time will be no longer than some amount, and that the propagation time will be no longer than a certain amount, but unless the hold time is zero or negative or a minimum propagation time is specified and it's longer than the required hold time, I don't think the data sheets actually specify correct operation for cascading latches. Certainly it's possible to have trouble when feeding the data output of a very fast chip into the data input of a slow chip with a long hold time.
One approach that's used with some protocols like SPI, and it's an approach I'd like to see used more, is to have the output stage of each latch change on the opposite clock edge from the input. I'm not sure why this approach isn't used more; while there are times when it would be unnecessary and wasteful (if one knows that the propagation time of the circuitry between two latches would be sufficient to satisfy the hold time of the downstream latch, having the output of the upstream latch change on the same clock edge as downstream latch is sampled would allow for higher clock speeds), it also makes it possible to guarantee the correctness of many circuits involving mixed logic families--something which may otherwise be difficult.