This is a pretty difficult accuracy/precision to hit.
First of all, according to the datasheet, you can't have a period on that pin of less than 20 ns, so that is a max frequency of 50 MHz. This is from Table 17-8 of the datasheet. So, 60 MHz is out.
But more importantly, you are trying to get a timing accuracy of 100 Hz / 60 MHz, this is 1.7 ppm accuracy. Or if you just want consistency, it's 1.7 ppm frequency stability. Most crystals are at least +/- 20 ppm stability. The smallest I could find immediately was a +/- 9. So that is a tight timing control.
However, let's say you could get a crystal and 50 MHz is good enough. Here is a quick clock path drawing based on the datasheet Figure 6-1 that shows how to configure the timer
Read 6.2.1 to see the limits that you must adhere to. In summary, it just says you need to have on the block that says "SYNC 2 cycles" a high time of at least 2*Tosc + 20ns, and a low time of the same. For a 13 MHz clock, this gives a max frequency of about 350 kHz. Note that this is after the prescaler, so the real limit is when you use the max prescaler setting: 256 * 350 kHz = 89 MHz. This is easily over the 50 MHz limit by the pin so you are good.
The required accuracy (within 100 Hz at 50 MHz) suggests being able to differentiate period differences of
$$\frac{1}{50MHz} - \frac{1}{50MHz + 100 Hz} = 40 femtoseconds!$$
The way to be able to get this small of a differentiation is to measure how long a large number of counts takes. This is perhaps overdoing it, but if this is all the processor is doing, I would want something like 10 us to make sure I had plenty of time to sample the data. This allows some error for the time the code takes. You could do it in less, but you would have to be more careful with your timing (count instruction cycles, etc). If you did about 0.5 billion counts, then a 10 us delay would only give a 50 Hz error. This means you would have to sample for nominally 10 seconds. The tighter your code timing, the more easily you can reduce the sample time.
