Hi I am not an Electrical Engineer but need to know something about Memory address ranges. I need to calculate address range of each memory chip(62256) from let suppose bank 1 in below diagram. How can I do this ?
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1\$\begingroup\$ Is this a homework question? If so, you need to show what you have worked out so far. \$\endgroup\$– tcrosleyCommented Jan 9, 2015 at 8:38
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\$\begingroup\$ Can you explain why you want to know? The addresses used on the bus will be physical addresses which may not map directly to addresses in software. If you're thinking about making a memory test program or something you need to check carefully how addressing works for your chosen processor architecture/tools. \$\endgroup\$– WillCommented Jan 9, 2015 at 11:34
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2 Answers
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For this, you need to see the 74LS244 and 74LS138 datasheets and work out which combinations of A15...A19 give chip selects to which chip. Each 62256 has 256 kilobits, which is 32 kilobytes.
So, First you think that A[19:15] = '00000'. That's the first 32KB memory block. Trace the states of the 74LS244 outputs for that combination. Then trace the outputs of the 74LS138's for that combination. The memory chip that gets a '0' in its chip select is activated for that memory region. Then continue from there, you'll soon figure it out.
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\$\begingroup\$ Something fundamentally wrong with the answer? \$\endgroup\$– PkPCommented Jan 9, 2015 at 9:32
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\$\begingroup\$ Nope, I believed the 62256 pinouts on the drawing. Mea culpa. :-( I'll edit your answer innocuously so I can upvote it. \$\endgroup\$ Commented Jan 9, 2015 at 9:54
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If each chip had only one address line, then when that line was low the 8 bit data byte (D0 - D7) at address \$ \ 0 \$ would be available to either read from or write to.
Then, if the address line went high, the 8 bit byte at address\$ \ 1\$ one would be available to either read from or write to.
If there were two address lines, then there would be four data locations accessible; 3 addresses would correspond to 8 data locations, 4 to 16, and so on in a binary progression where the number of data locations would correspond to \$ \ 2^n \$ addresses, with \$ \ ^n \$ being the number of address lines.
There's an error in the drawing in that the 62256 has 15 address lines, not 14, and since there are 15 address lines per chip, the address range (the number of data locations per chip) would be \$ \ 2^{15} \$, or 32768 bytes.
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\$\begingroup\$ KM62256 has 15 address lines, A[14:0]. I don't know why A0 is missing from the picture. It looks a little like it's redrawn from some ancient 68000 memory bus and some errors have crept in. Those had A0 missing, A[15:1] of CPU connected to A[14:0] of KM62256, high side memories connected to D[15:8] and low side memories to D[7:0]. I'm just saying this because the resemblance is so striking. I don't know where this schematic has come from. \$\endgroup\$– PkPCommented Jan 9, 2015 at 9:25