In many test benches I see the following pattern for clock generation:
process begin clk <= '0'; wait for 10 NS; clk <= '1'; wait for 10 NS; end process;
On other cases I see:
clk <= not clk after 10 ns;
The later is said to be better, because it is scheduled before any process is executed, and thus signals that are changed synchronously to the clk edge are handled properly. The following sections from the LRM may seem to support this theory:
Page 169: 12.6.4 The simulation cycle A simulation cycle consists of the following steps:
- b) Each active explicit signal in the model is updated. (Events may occur on signals as a result.)
This should be the signals with a new projected value such as signals delayed by the
- d) For each process P, if P is currently sensitive to a signal S and if an event has occurred on S in this simulation cycle, then P resumes.
That would be most of the logic to be simulated
- e) Each nonpostponed process that has resumed in the current simulation cycle is executed until it suspends.
And now all processes that are suspended by a
wait for are executed.
- Is the
aftermethod always superior to the
- Does it help to prevent the problems synchronously set input signals?