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I want to use a JK flip flop in order to create a toggle output. It is clear that both J and K should be set to 1, as well as the Preset and Clear inputs.

In some schematics, a Monostable 555 followed by a NOT gate, appears to connect with the Clear.

I think that the Mono creates a pulse and after that it stops, so connected with a NOT gate, the output of the NOT gate should create a power "gap" and after that it should continue powering the Clear input.

It looks like a delay in inserted, in order to power up first the Preset input and second the Clear input.

If that is the case, it's OK, even though I can't understand the reason for that. Yet, I have created a simple toggle circuit without a time delay, thus both Preset and Clear are power simultaneously, and it seems to work fine.

Actually, I have created two circuit versions, with one and two flip flops, meaning one and two outputs, and both work fine.

Do I miss something there? The same question goes with the T flip flop as well.

Thank you.

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For a typical flip-flop, you only need a few ns of delay after power-up to set the logic. If the input to the flip-flop has a Schmitt trigger design, you can use a simple R-C divider across the rails. Connect the reset line to the center of the divider. If you need a high value for reset and a low for operation, connect the resistor to ground and the cap to +Vcc. It's the reverse for opposite logic.

The way it works is that for the power-on transient, the capacitor behaves as a short circuit and the voltage across the cap will be near-zero for a while after power comes on. Then, as the cap charges, the voltage as the midpoint moves (slowly) to the other rail. This slow RC behaviour is why you need Schmitt inputs on the signal.

If you need fast reset for power cycling, you can put a reverse-biased diode across the cap to encourage fast discharge when power is removed.

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Your lack of reference to the type of JK FF prevents a specific answer, however in general you want the J & K inputs connected to a logic 1. The preset and clear inputs will be either active-low or active-high.

In either case, assuming you wish to clear the FF, you want to drive the clear input active during initialization, and to inactive later. The preset input should remain inactive always.

The 74HC73, for example, has only a reset input, and it's active low. So you want to generate a pulse that lasts for some small amount of time after the power has reached the proper level, and that pulse should be low, followed by a high level forever. A 4027 has both inputs, and they are active-high, so you would tie the preset input low and pulse the reset input high at power-on.

By the way, 555's and RC circuits are not reliable ways to reset logic. I advise using a proper reset chip that has a voltage reference built in and a time delay on the output pulse.

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  • \$\begingroup\$ I neglected to mention that I used an SN74LS76AN \$\endgroup\$ – user3060854 Jan 11 '15 at 19:39
  • \$\begingroup\$ The 74LS76 (like most 74xx series) has active low inputs, so like the 74HC73 (drive the /CLR input low momentarily) and since it has a preset input, tie the /PRE input high permanently. \$\endgroup\$ – Spehro Pefhany Jan 11 '15 at 19:49
  • \$\begingroup\$ I goggled a bit for a reset chip but fount nothing. Could you possibly recommend such a chip? \$\endgroup\$ – user3060854 Jan 11 '15 at 20:29
  • \$\begingroup\$ Look for supervisory chip or reset chip. One example would be the ADM809 which is active-low and provides a 140ms reset pulse. You'd probably want the 4.63V version. \$\endgroup\$ – Spehro Pefhany Jan 11 '15 at 20:33

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