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I'm trying to connect multiple components (same components) to an FPGA output. The FPGA runs at 30Mhz and transmitting both a clock and data on lines connected to these similar components.

Each component is located in a different distance from the FPGA where the shortest is 10mm and the longest is 300mm

  1. When the difference is 290mm and the frequency is 30Mhz, do I need to worry about one signal reaching before the other?
  2. Is there a rule of thumb or a way to calculate what is the maximum difference in distances that is allowed for a specific signal frequency?
  3. Should the trace be thicker or thinner for fast data? will 8mil do?

PCB is flex 2-layer, no right-angle folds, 1OZ copper, signal can be 3.3V or 5.0V

Gilad.

enter image description here

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    \$\begingroup\$ With a wavelength in air of ~10m I don't think you have much to worry about there... It's only when the wavelength is less than (or close to) the transmission distance that you need to worry. Oh, and 30MHz is not fast. \$\endgroup\$ – Majenko Jan 12 '15 at 23:41
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    \$\begingroup\$ @Majenko 30 MHz is fast enough that you could screw up if you made a totally naive design. \$\endgroup\$ – The Photon Jan 13 '15 at 0:03
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    \$\begingroup\$ @ThePhoton Well, yes, if you did something stupid, certainly. I'd be more concerned about output drive strength and input capacitance than impedance matching. \$\endgroup\$ – Majenko Jan 13 '15 at 0:10
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  • When the difference is 290mm and the frequency is 30Mhz, do I need to worry about one signal reaching before the other?
  • Is there a rule of thumb or a way to calculate what is the maximum difference in distances that is allowed for a specific signal frequency?

The propagation velocity is given roughly by the dielectric constant of the material of your pcb

$$ v \approx \frac{c}{\sqrt{\epsilon_r}}$$

(Actually it will be a bit higher because some of the signal travels in air rather than in the PCB)

For FR4, \$\epsilon_r\$ is roughly 4.5 (+/- 0.5). For flex material, you'll need to check the datasheet of your material.

The difference in time-of-arrival is just the difference in trace length divided by the velocity.

And the rule-of-thumb in a digital design is that you need to satisfy the set-up and hold times for all the logic you are sending signals to. In some cases, you may also need to keep your clocks in sync between the different load components, but that is a design-specific requirement.

Should the trace be thicker or thinner for fast data? will 8mil do?

For 30 MHz with a maximum trace length of 300 mm, the trace width is not critical.

P.S.

For this design, if you don't have any special syncronization requirements, I'd rather minimize the total capacitance of the trace by running a single track that goes near all 7 loads, and make a short stub to each load, rather than have very long stubs leading to the loads from the point of origin.

P.P.S.

Your wavelength and trace length are in the realm of needing to worry about radiated emissions if you are planning to use or sell this in the US or Europe. Make sure you have a well-defined return path for each signal path, and remember the critical distances for EMI purposes are more realted to the signal's rise and fall times than on the repetition frequency.

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Follow The Photon's good advice, but I'll also add:

  • Use series termination resistors at the end of each stub closest to the slave device. Recommended value is typically 22-100R.
  • Have a read of the relevant configuration instructions for your FPGA; Xilinx (for example) goes into great detail about how to safely and reliably route the signals for their JTAG implementation. That advice should be generally applicable to any high-speed synchronous transfer.
  • Use differential signalling if you can; properly routed differential signals are far, far less likely to cause or be subject to interference.
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