JK Flip Flop toggle action

How does toggle action in a JK flip flop change to alternate states? When both inputs are 1 ,the output of nor gates is forced to 0,then how come they toggle ? simulate this circuit – Schematic created using CircuitLab For example When both J=K=1; the input NOR gate-1 & 2 respectively 0 & 1.When one of the input of Nor gate is one the output will be zero.so when Nor gate-2 output change to zero then both input of NOR gate-1 will be zero so output of NOR gate-1 changed to one.As per your point of view both q & q bar zero may happen between toggle states (I mean it may happen @ time between NOR gate-1 take Q bar=0 output & changed NOR gate-1 output equal to zero).But stable final output will be toggle one.

Sorry friend if any wrong in my logic.Kindly please let me know if any..

• But how both the inputs to the first nor gate became 0 ? Feedback input is 1, isn't it? – Alex Grahm Jan 13 '15 at 13:37
• Yes you are partially right.After clock trigger edge the output of AND gate-1 & 2 is as I told early AND-1=0;AND-2=1.This state can't change until next trigger edge come.As your point of you even NOR gate-1 take previous state of feedback input "q bar=1" the output of that Nor gate-1 becomes zero.But it will change after state change of "current state of q bar=0" now current state of that feedback input is logic-0.So,Now the output of NOR gate-1 become logic-1.Can you able to understand now Alex? – victory Jan 14 '15 at 7:30

To understand flip flop type circuits you need to carefully consider what comes before and after each state change. You might also need to see the whole view of the internal logic gates, as some can be very complex. Without that you may just need to accept the operation as shown in the state tables. Another important idea is to learn the way that a pair of logic gates use feedback to latch up.

Here is some more info from wiki: http://en.wikibooks.org/wiki/Practical_Electronics/Flip-flops

• Here's another specifically on the JK flip flop. It shows how the Clk input affects the logic: electronics-tutorials.ws/sequential/seq_2.html Using all Nand gates for the latches is very similar to using the Nor gates. – Nedd Jan 13 '15 at 12:43

One common hard to see issues for a simplified flip flop is what state comes first. For the above set of gates you can not really determine the initial state, but you need to assume one fixed state at the start. What you select is not so important because the sequence repeats itself continuously (for the toggle mode).

Once you specify an initial state you can determine all of the following states after a new clock edge or other JK inputs.

On more sophisticated circuits (ICs) the start up can be defined by the manufacturer using extra gates and delay circuits, (this is also where the extra Set and Reset inputs can be used). One thing that is always fixed, the outputs of each latch pair will always be opposites.

Try looking at this diagram and note that in an earlier answer the output feedback connections are shown incorrectly thus they won't toggle as you suspected in your comment: - Information taken from here

• But your example is using NAND gates. The previous examples and the circuit which I studied is using AND gates and NOR gates. I would be thankful to you, if you could explain me using the image in this link.. ibiblio.org/kuphaldt/electricCircuits/Digital/04196.png – Alex Grahm Jan 13 '15 at 17:25
• If you understand how a JK FF works from the image I have posted then convert to NOR gates. If you don't understand the image then me drawing it as NOR gates won't be useful to you either. – Andy aka Jan 14 '15 at 9:05
• I wonder why so many pieces about JK flip flops include circuit diagrams that won't work in practical usage? The above circuit only works if the clock pulse lasts long enough for its effects to propagate through both the left and right gates once, but not long enough for it to propagate through the left gates a second time. – supercat Feb 12 '15 at 23:38