I'm receiving a "design contains no instances" error but I'm unable to find out the cause of the error despite Googling a lot and trying out the solutions suggested on forums. Below is a report summary for the design, any ideas?

WARNING:NgdBuild:578 - Design contains no instances.
*                           Partition Report                            *

Partition Implementation Status

  No Partitions were found in this design.


*                            Design Summary                             *

Clock Information:
No clock signals found in this design

Asynchronous Control Signals Information:
No asynchronous control signals found in this design

Timing Summary:
Speed Grade: -3

   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: No path found


Process "Synthesize - XST" completed successfully

Started : "Translate".
Running ngdbuild...
Command Line: ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc6vlx240t-ff1156-3 "HCORDIC_Main.ngc" HCORDIC_Main.ngd

Command Line: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/ngdbuild -intstyle
ise -dd _ngo -nt timestamp -i -p xc6vlx240t-ff1156-3 HCORDIC_Main.ngc

Reading NGO file "/home/a/Downloads/Untitled
Folder/Multiplexer/HCORDIC_Main.ngc" ...
Loading design module "/home/a/Downloads/Untitled
WARNING:NgdBuild:578 - Design contains no instances.
Gathering constraint information from source properties...

Resolving constraint associations...
Checking Constraint Associations...

Checking expanded design ...

Partition Implementation Status

  No Partitions were found in this design.


NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   1

Writing NGD file "HCORDIC_Main.ngd" ...
Total REAL time to NGDBUILD completion:  5 sec
Total CPU time to NGDBUILD completion:   4 sec

Writing NGDBUILD log file "HCORDIC_Main.bld"...


Process "Translate" completed successfully

Started : "Map".
Running map...
Command Line: map -intstyle ise -p xc6vlx240t-ff1156-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o HCORDIC_Main_map.ncd HCORDIC_Main.ngd HCORDIC_Main.pcf
Using target part "6vlx240tff1156-3".
**ERROR:Map:116 - The design is empty.  No processing will be done.
ERROR:Map:52 - Problem encountered processing RPMs.**
  • 2
    \$\begingroup\$ The problem is clear: no instances. Does your VHDL script contain any instances? Why don't you post your code? \$\endgroup\$
    – Nazar
    Commented Jan 15, 2015 at 13:06

1 Answer 1


The problem to the question raised by me was actually an error in the connection of the output port in my case [can also be any i/o port]

Thus in the instantiated module there was a connection made by wire using verilog coding in the top level file but in the module itself that output was not assigned any value.

And since these outputs were supposed to be an input in another instantiated module, Xilinx ISE considered it to be unconnected thereby, during the optimization step these modules were removed, leaving the design with no instances.


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