I am using a SAS expander IC. In the datasheet, it is given to use a 150 MHz LVPECL clock with specifications as attached in the snapshot.

Can somebody please explain how to use common mode & differential specifications while choosing a LVPECL clock.

enter image description here


Basically you need to feed the chip with a clock. The clock needs to be dual phase or differential i.e. clock and clock-bar.

Both these signals (clock and clock-bar) should have an average DC level between 0.1 volts and 3.0 volts).

The differential amplitude of 0.18 to 2.4 volts translates to a single ended amplitude of 0.09 volts to 1.2 volts for either clock or clock-bar.

Rise and fall times - need to be no more than 2ns.

Input duty cycle is basically stating that a 50:50 on-off ratio is preferred but if this ranges between 40% and 60% then it should be OK.

  • \$\begingroup\$ The common mode range of the input generally has to include the amplitude of the differential signal. So you would not be able to apply a clock with average DC level of 3.0 volts with an amplitude over zero volts. If the average DC level was 2.5V then the input amplitude could not exceed 0.5V above the DC level. \$\endgroup\$ – Michael Karas Jan 15 '15 at 16:50
  • \$\begingroup\$ Does this common mode voltage i.e. average DC level is the supply voltage Vcc I have to look @ in the datasheet? \$\endgroup\$ – Oshi Jan 16 '15 at 4:21
  • \$\begingroup\$ Without spilling the beans on the device nobody can say. \$\endgroup\$ – Andy aka Jan 16 '15 at 8:34
  • \$\begingroup\$ Can this oscillator be used for above specification ::- txccrystal.com/images/pdf/bb.pdf \$\endgroup\$ – Oshi Jan 16 '15 at 8:59
  • \$\begingroup\$ It's the receiving device that needs to be analysed. The clock data sheet says LVPECL and it may be compatible but it might need capacitively coupling and termination resistors adding. It can be tricky to analyse. \$\endgroup\$ – Andy aka Jan 16 '15 at 9:26

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