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I used Quartus II Magawizard to ask for a two port RAM(one read and one write). The addresses are correct but the data out is always z. Can some one help me with this problem? I have stuck here for a whole day...

I instantiate and connect the RAM as following:

 RAM0 ra(
    .clock(clk),
    .rdaddress(raddr_a),
    .wraddress(waddr_a),
    .wren(we_a),
    .q(q_a),
    .data(data_a));

and modelsim the RAM: wave form for RAM ra

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  • \$\begingroup\$ It should still show at least undefined, not z. Do you get any compilation warnings from Modelsim? \$\endgroup\$ – apalopohapa Jan 16 '15 at 3:18
  • \$\begingroup\$ Quartis also generates a black box file (..._bb.v), make sure you're not simulating that one. \$\endgroup\$ – apalopohapa Jan 16 '15 at 3:57
  • \$\begingroup\$ Problem solved! Thank you very much! I connected the output port q to a port with different width... that is the problem. I should never ignore any warnings! Thank you! \$\endgroup\$ – SH1991 Jan 16 '15 at 14:37
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From the poster:

Finally(maybe temporarily) solve this problem.

Tips: New a modelsim project instead of vsim files directly. Look at all the warnings, see whether port width mismatch. Do not include _bb.v file in the work library or you will get high-z output. Add library if you use third-party src or magawizard.

Thanks to apalopohapa!

From the comments:

It should still show at least undefined, not z. Do you get any compilation warnings from Modelsim? – apalopohapa

Quartus also generates a black box file (..._bb.v), make sure you're not simulating that one. – apalopohapa

Problem solved! Thank you very much! I connected the output port q to a port with different width... that is the problem. I should never ignore any warnings! Thank you! – SH1991

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  • \$\begingroup\$ Thanks for reply! According to the auto-generated RAM.v file, the two ports are write port(wraddress, data) and read address(rdaddress, q), and rden signal is missing... module RAM1 ( clock, data, rdaddress, wraddress, wren, q); \$\endgroup\$ – SH1991 Jan 16 '15 at 2:50
  • \$\begingroup\$ Perhaps it is a single port ram. Try de-asserting wren and see if q starts showing data. \$\endgroup\$ – apalopohapa Jan 16 '15 at 2:58
  • \$\begingroup\$ I tried to disable wren after several clk, still no q... May be the data is not write into ram successfully? \$\endgroup\$ – SH1991 Jan 16 '15 at 3:05
  • \$\begingroup\$ @SH1991 It should still show at least undefined, not z. Do you get any compilation warnings from Modelsim? \$\endgroup\$ – apalopohapa Jan 16 '15 at 3:15
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\$\begingroup\$

Finally(maybe temporarily) solve this problem.

Tips: New a modelsim project instead of vsim files directly. Look at all the warnings, see whether port width mismatch. Do not include _bb.v file in the work library or you will get high-z output. Add library if you use third-party src or magawizard.

Thanks to apalopohapa!

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