# Verilog megawizard RAM not read

I used Quartus II Magawizard to ask for a two port RAM(one read and one write). The addresses are correct but the data out is always z. Can some one help me with this problem? I have stuck here for a whole day...

I instantiate and connect the RAM as following:

 RAM0 ra(
.clock(clk),
.wren(we_a),
.q(q_a),
.data(data_a));


and modelsim the RAM:

• It should still show at least undefined, not z. Do you get any compilation warnings from Modelsim? – apalopohapa Jan 16 '15 at 3:18
• Quartis also generates a black box file (..._bb.v), make sure you're not simulating that one. – apalopohapa Jan 16 '15 at 3:57
• Problem solved! Thank you very much! I connected the output port q to a port with different width... that is the problem. I should never ignore any warnings! Thank you! – SH1991 Jan 16 '15 at 14:37

From the poster:

Finally(maybe temporarily) solve this problem.

Tips: New a modelsim project instead of vsim files directly. Look at all the warnings, see whether port width mismatch. Do not include _bb.v file in the work library or you will get high-z output. Add library if you use third-party src or magawizard.

Thanks to apalopohapa!

It should still show at least undefined, not z. Do you get any compilation warnings from Modelsim? – apalopohapa

Quartus also generates a black box file (..._bb.v), make sure you're not simulating that one. – apalopohapa

Problem solved! Thank you very much! I connected the output port q to a port with different width... that is the problem. I should never ignore any warnings! Thank you! – SH1991

• Thanks for reply! According to the auto-generated RAM.v file, the two ports are write port(wraddress, data) and read address(rdaddress, q), and rden signal is missing... module RAM1 ( clock, data, rdaddress, wraddress, wren, q); – SH1991 Jan 16 '15 at 2:50
• Perhaps it is a single port ram. Try de-asserting wren and see if q starts showing data. – apalopohapa Jan 16 '15 at 2:58
• I tried to disable wren after several clk, still no q... May be the data is not write into ram successfully? – SH1991 Jan 16 '15 at 3:05
• @SH1991 It should still show at least undefined, not z. Do you get any compilation warnings from Modelsim? – apalopohapa Jan 16 '15 at 3:15

Finally(maybe temporarily) solve this problem.

Tips: New a modelsim project instead of vsim files directly. Look at all the warnings, see whether port width mismatch. Do not include _bb.v file in the work library or you will get high-z output. Add library if you use third-party src or magawizard.

Thanks to apalopohapa!