I used Quartus II Magawizard to ask for a two port RAM(one read and one write). The addresses are correct but the data out is always z. Can some one help me with this problem? I have stuck here for a whole day...
I instantiate and connect the RAM as following:
RAM0 ra( .clock(clk), .rdaddress(raddr_a), .wraddress(waddr_a), .wren(we_a), .q(q_a), .data(data_a));
and modelsim the RAM: