When your design includes control registers that are set/read on a dedicated clock domain (SPI or I2C etc), how do you usually deal with those?
Do you keep them on their own clock domain and
false_paththem to wherever they go, not worrying too much about metastability?
Or maybe take loads of care to make sure there are meta-stable flops on each domain crossing, pushing up area in the case of large reg-maps? And if they span out into multiple clock domains, well, you just hang multiple synchronisers off the control line?
Any other suggestions I'm missing?