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How exactly are pull-up and pull-down networks defined in the context of CMOS logic? Also, why are PMOS's used for pull-up networks and NMOS's for pull-down networks, instead of the opposite?

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PullUp and PullDown

Pullup - a network that provides a low resistance path to Vdd when output is logic '1' and provides a high resistance to Vdd otherwise.

Pulldown - a network that provides a low resistance path to Gnd when output is logic '0' and provides a high resistance to Gnd otherwise.

What if PMOS is used in pullDown and NMOS in PullUp?

If we use PMOS in pull down network, then its gate terminal should be provided with a negative voltage. Similarly if we use NMOS in pull up network, then its gate terminal should be provided with a voltage that is more positive than Vdd.

So the voltages corresponding to logic states at input are different from that at output. Hence two such 'CMOS' gates can not be interfaced directly.

In other words, \$V_{OH} < V_{IH}\$ and \$V_{OL} > V_{IL}\$ which will result in negative noise margin. And hence this logic family would be incompatible with itself.

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Pullups pull the voltage up towards more positive values, and pulldowns pull the voltage down towards more negative values.

PEMOSFETs have a negative threshold to turn on, so putting them in the pullup role means that they will conduct when their gate voltage drops, and vice versa for NEMOSFETs. Putting them both in series in the same circuit and tying the gates together results in a natural inverter.

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The basic reason is similar to using an NPN verses a PNP transistor.

In a simple approximation the PMOS and NMOS parts work by shorting the Drain and Source pins, when the Gate voltage is satisfied.

For NMOS the Gate is satisfied when it goes high. For PMOS the Gate is satisfied when it goes low. (In relation to the Source pin)

For a NMOS part the Source pin must be connected at the low level, so when turned on the Drain pin can only "pull down" to that same low level.

For a PMOS part the Source pin must be connected at the high level, so when turned on the Drain pin can only "pull up" to that same high level.

When you have one NMOS and one PMOS connected in a push-pull arrangement, (Gate to Gate, Drain to Drain, one Source at high, and one Source at low), putting a square wave onto the Gates will give a similar square wave (a pull up then a pull down) on the Drains.

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