I am attempting to build a 3-bit 0-5V flash ADC using two TL074 quad op amps and a 74LS148 active-low priority encoder.
The circuit is fairly simple. 8 100K resistors are connected in series between 0V and +5V, with each node between connected to the inverting input of one of 7 op amps, providing 7 reference voltages for the comparators, equally spread between the supply rails. The input is connected to the non-inverting inputs of all 7 op amps. The op amps are also supplied from the 0V and +5V. Each op amp's output sits at about +1.4V until the input goes above its respective reference voltage, at which point it snaps up to about +3.6V.
My thought was that these could then directly drive the 74LS148 inputs (1 - 7, in reverse order, with input 0 grounded). If I interpret the voltages by hand according to the 74LS148's function table, I should get the (active-high) output I want. However, it seems that the inputs from the op amps are always being seen as high, even when they are at the low +1.4V state. (I do see occasional glitches where the outputs jump to a state other than all high.)
Is that +1.4V simply above or too near the logic threshold for the 74LS family? Research suggests not, but maybe I read something wrong? Or, are the output pins of the TL07x perhaps unable to sink enough current to drive the 74LS inputs low? Or is it something else?
Note that I also have -12V and +12V supplies available in this circuit, in case the op amp supply rails need to be changed.