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I need to implement a 2:1 multiplexer for 8-bit data. That is: as inputs it should take two 8-bit numbers and a Select line; and as output an 8-bit number.

I could use two 74HC(T)157s (this is a quad 2-input multiplexer), however, because of its pinout (see below), implementing an 8-bit 2:1 multiplexer would cause a mess on the PCB, and I will probably use several multiplexers in this project.

What is the common way to implement more-than-one-bit (2:1) multiplexers on a PCB? Are there readymade ICs for this (I couldn't find them) or is there a way to keep the PCB uncluttered?

Since I will be home-etching the prints I'm unfortunately rather limited to one layer. The final project should be a home-made CPU of discrete components (really).


This is the pinout of the chip I mentioned. For example, 1I0 and 1I1 are inputs for 1Y. S is the common selector.

enter image description here

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  • \$\begingroup\$ Using '157s is the "standard" answer. Many DRAM controllers were built with exactly that technology. The PCB layout can't always be "pretty" -- just deal with it. \$\endgroup\$ – Dave Tweed Jan 17 '15 at 21:45
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    \$\begingroup\$ First, presumably you've already looked at assigning channels by geometric convenience rather than number and decided that doesn't solve your problem. A CPLD could give you a lot of pinout flexiblity, but perhaps would be "cheating" by your goals. On the novel front, if your delay budget is generous an (E)PROM loaded with a suitable truth table to use address lines as channel and select inputs could be a solution. A more off-the-shelf solution might be to use tri-state buffers on each side, with only one enabled at a time, or even at an extreme, open-collector logic gates and a pullup. \$\endgroup\$ – Chris Stratton Jan 17 '15 at 22:06
  • \$\begingroup\$ @ChrisStratton tri-state buffers or open collectors are excellent ideas. I didn't think of them at first because our teacher had explained the disadvantages of using them (some kind of unexpected behaviour if I remember correctly). However, he was talking about design on the chip, and this probably won't cause any issues here. A CPLD would indeed work, I also thought already of a microcontroller, but yeah, that's cheating. However, maybe you could turn this into an answer so that I can show my appreciation? :) \$\endgroup\$ – user17592 Jan 17 '15 at 22:28
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    \$\begingroup\$ My first reaction was "oh, how hard could it be?" but after a minute of finger tracing I agree that this would be very hard to route. \$\endgroup\$ – Greg d'Eon Jan 17 '15 at 22:43
  • \$\begingroup\$ Tristate sounds good, and the routing is nice, but you lose on the package size due to pin count. 2 157s require 2 16-pin packages, but 2 8-bit bus drivers will require 2 20-pin packages, in addition to whatever you need to produce 2 select lines rather than 1 (since the enable lines need to be complementary. I'm not sure which would take more real estate. \$\endgroup\$ – WhatRoughBeast Jan 17 '15 at 23:14
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First, presumably you've already looked at assigning channels by geometric convenience rather than number and decided that doesn't solve your problem.

A CPLD could give you a lot of pinout flexiblity, but perhaps would be "cheating" by your goals (though there were board-level mainframe CPUs that used early PALs).

On the novel front, if your delay budget is generous an (E)PROM loaded with a suitable truth table to use address lines as channel and select inputs could be a solution. Perhaps you are already using something similar to hold a table for instruction decode or even microcode.

A more off-the-shelf solution might be to use tri-state buffers on each side, with only one enabled at a time, or even at an extreme, open-collector logic gates and a pullup.

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  • \$\begingroup\$ If there's room I second the discreet solution. That should produce a great layout at least. \$\endgroup\$ – Vladimir Cravero Jan 17 '15 at 22:44
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The 74HC298A is more expensive (Digikey has it for $5.81, while the 157 is around $0.70) but it was designed for 4-bit data lines (instead of 4 1-bit data lines), so it has a much friendlier layout:

Pinout of the 298A

You may be able to route the traces for input 2 upwards and squeeze C1 between D1 and D2. With some luck, this might extend to two of these side-by-side.

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  • \$\begingroup\$ I didn't see that chip before, thanks very much. I think I'm still gonna go with Chris's open collector / tri-state buffer idea looking at the costs (I have loads of suitable transistors laying around), but I'll sure keep an eye on this chip for other designs. \$\endgroup\$ – user17592 Jan 18 '15 at 11:04
  • \$\begingroup\$ That makes a lot of sense. Thanks for the feedback - this was definitely quite far down on the list and I could see why you wouldn't spot it. \$\endgroup\$ – Greg d'Eon Jan 18 '15 at 12:24
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How about a pair of 74LS541s? or 74LS245s? May depend on precisely how you are driving them, they're both cheap enough. I believe you're doomed to a set of jumpers either way.

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  • \$\begingroup\$ That would be the 541, I'm not going to need two-way. Thanks very much. I think I'm going to use a design similar to its internal circuit (it will likely keep the PCB design easier and I have loads of suitable transistors lying around). \$\endgroup\$ – user17592 Jan 18 '15 at 11:07
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Probably the best alternative you will find is a sn74LS399.

But to be honest, you should just do two layers. You are going to have serious issues getting power and ground to all of your chips with a 1 layer. It isn't that hard with home etching, just be careful with lining everything up. There are a lot of examples online of how to do this.

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