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I'm trying to design an accelerated CPU (65816) for the Apple IIGS by using a high speed ARM processor combined with a software emulator + software emulated cache. The CPU I'm using is the LPC4300 series, which runs at a high speed (200+ MHz) and also has large amounts of internal SRAM which can be used as the emulated cache.

The problem is that the LPC4300 is based on 3.3V logic, while the IIGS motherboard expects 5V. For most of the pins, I can use a standard bus-transceiver to perform the 3.3-5V conversion. Even most bi-directional pins (for example, the data pins on the CPU) can be handled in this fashion, so long as the bus transceiver has 3-state outputs and enable and direction pins. The problem is with the 'RDY' pin on the 65816, which is both bi-directional but does not have any other pin indicating the direction. The function of the 'RDY' pin (as quoted from the datasheet) is as follows:

2.24 Ready (RDY)

The Ready is a bi-directional signal. When it is an output it indicates that a Wait for Interrupt instruction has been executed halting operation of the microprocessor. A low input logic level will halt the microprocessor in its current state. Returning RDY to the active high state releases the microprocessor to continue processing following the next PHI2 negative transition. The RDY signal is internally pulled low following the execution of a Wait for Interrupt instruction, and then returned to the high state when a RESB, ABORTB, NMIB, or IRQB external interrupt is active. This feature may be used to reduce interrupt latency by executing the WAI instruction and waiting for an interrupt to begin processing. If the IRQB Disable flag has been set, the next instruction will be executed when the IRQB occurs. The processor will not stop after a WAI instruction if RDY has been forced to a high state. The STP instruction has no effect on RDY. The RDY pin has an active pull-up and when outputting a low level, the pull-up is turned off to reduce power. The RDY pin can be wired ORed

I do not see a way to use a standard logic level converter here, since it seems that the direction of RDY is not reflected anywhere else. Any suggestions or ideas?

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One simple and flexible solution could be mapping the legacy signal to two signals on your module - one a dedicated input, the other a (sometimes) output.

You'll often see something somewhat similar in organization done with FPGA designs, where the internal signals have dedicated direction, and a tri-state buffer is applied to join them to an external bidirectional bus only at the level of the actual I/O pin blocks, controlled by an enable signal generated internally.

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  • \$\begingroup\$ I thought about this, but the 5V side of the converter would also need to be able to pull the 3.3V side low despite the 'output' pin trying to drive high - so that the 'input' pin can read an external device trying to pull the RDY signal down. Or the output pin on the 3.3V side could be disabled, but then the 5V side of RDY would need to be latched high somehow... \$\endgroup\$ – Zuofu Jan 18 '15 at 0:43
  • \$\begingroup\$ One way is to have your output be open collector, or more specifically, a pullup to 5v at the far side of an open-collector level translator (which could be the classic mosfet circuit). If you want to fully emulate the original, you can add something to disable the pullup when driving low. \$\endgroup\$ – Chris Stratton Jan 18 '15 at 0:53
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You could use the standard approach used to connect two I2C busses together: a logic-level MOSFET. Here is one example.

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I'd use a TXB0108 (or possibly one of it's lower pin count cousins), an 8-channel bidirectional logic level translator.

It has a 1.2-3.6V 'A' side and a 1.65-5.5V 'B' side and does automatic (i.e. no direction input required) bidirectional conversion at up to 100MHz between the A and B sides.\

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I'd never looked for one in the past (I've never needed to do a single line) but there is a TXB0101 that might be a slightly better fit.

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  • \$\begingroup\$ This is a cool part, I wonder how it reacts to a high impedance signal on the 3.3V side though - if it would latch the last state or flip out... \$\endgroup\$ – Zuofu Jan 18 '15 at 0:44
  • \$\begingroup\$ @Zuofu That had never occurred to me. However. I've used them (amongst other places) on bidirectional data buses before without issues. Also, TI are pretty reliable as a rule. \$\endgroup\$ – markt Jan 18 '15 at 0:48

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