I am working with a Cyclone board. A basic code to assign every switch to the red leds is:

module part2 (SW, LEDR, LEDG);

    input [17:0] SW;    
    output [17:0] LEDR;

    assign LEDR = SW;


But I need the value of SW[17] to do some output operations, I don't understand how to store it in an subarray... (I also need the inputs of SW[7:0] and SW[15:8] ). How can I achieve this?

I just started with Verilog today and I am confused.


You are looking for the slice operator. You can read up on verilog in lots of places to get more details. Here's a decent one.

Here's just an idea of some of the things you can do. Read the tutorial at the link for more info.


  input [17:0] SW;    
  output [17:0] LEDR;
  output SINGLE_BIT_OUT;           // This is one bit.
  output [2:0] ANOTHER_ARRAY_OUT;  // This is 3 bits.
  output reg [3:0] REGISTERED_OUT; // A 4 bit registered output.

  assign LEDR = SW; 
  assign SINGLE_BIT_OUT = SW[17];       // Continuous 1 bit assignment.
  assign ANOTHER_ARRAY_OUT = SW[11:9];  // Continuous 3 bit assignment.

  // Or you can use an always block to do more fancy stuff
  always @(SW) begin
      if (SW[2:0] == 2'b000)
         REGISTERED_OUT = 4'b0010;  // Just put a constant to it in this case.
         REGISTERED_OUT = {1'b0, SW[2:0]};  // Or you can build assignments with slices like this.

| improve this answer | |
  • \$\begingroup\$ How do I represent "If SW[17] is turned off"? \$\endgroup\$ – JOX Jan 18 '15 at 6:01
  • \$\begingroup\$ if (~SW [17]) ... \$\endgroup\$ – caveman Jan 18 '15 at 6:10
  • \$\begingroup\$ For a single bit, they are actually equivalent. For wider slices, not so much. ~ is bitwise inversion. ! is logical not. \$\endgroup\$ – caveman Jan 18 '15 at 6:15
  • \$\begingroup\$ Can you please answer here? I have a more specific issue. electronics.stackexchange.com/questions/149711/… \$\endgroup\$ – JOX Jan 18 '15 at 6:18

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