How do for loops work in verilog? Why can't I achieve what I want?

This is my code for a simple 2-1 8 bit multiplexor, where SW[17] is my selector.

If it is on, show Y = SW[15:8], if it is off, show X = SW[7:0].

module part2 (SW, LEDR, LEDG);

input [17:0] SW; //inputs
output [17:0] LEDR; //light every switch
output [7:0] LEDG;  //byte desired

//All switches to red leds.
assign LEDR = SW;

//Green leds get the desired byte.
assign LEDG[0] = (~SW[17] & SW[0]) | (SW[17] & SW[8]);
assign LEDG[1] = (~SW[17] & SW[1]) | (SW[17] & SW[9]);
assign LEDG[2] = (~SW[17] & SW[2]) | (SW[17] & SW[10]);
assign LEDG[3] = (~SW[17] & SW[3]) | (SW[17] & SW[11]);
assign LEDG[4] = (~SW[17] & SW[4]) | (SW[17] & SW[12]);
assign LEDG[5] = (~SW[17] & SW[5]) | (SW[17] & SW[13]);
assign LEDG[6] = (~SW[17] & SW[6]) | (SW[17] & SW[14]);
assign LEDG[7] = (~SW[17] & SW[7]) | (SW[17] & SW[15]);

endmodule


This code is simple, but I am trying to optimise it and replace the 8 lines.

I wanted to use some sort of loop, but I failed:

integer index;
initial
begin
for(index = 0; index < 8; index  = index+1)
begin
assign LEDG[index] = (~SW[17] & SW[index]) | (SW[17] & SW[index+8]);
end
end


I also tried this, and I failed:

//Green leds get the desired byte.
always @(SW) begin
if (~SW[17])
assign LEDG = SW[7:0];
else
assign LEDG = SW[15:5];
end


I am getting an error saying that the left part of the assignment must have a variable data type.