This is my code for a simple 2-1 8 bit multiplexor, where SW[17] is my selector.

If it is on, show Y = SW[15:8], if it is off, show X = SW[7:0].

module part2 (SW, LEDR, LEDG);

    input [17:0] SW; //inputs
    output [17:0] LEDR; //light every switch
    output [7:0] LEDG;  //byte desired

    //All switches to red leds.
    assign LEDR = SW;       

    //Green leds get the desired byte.
    assign LEDG[0] = (~SW[17] & SW[0]) | (SW[17] & SW[8]);
    assign LEDG[1] = (~SW[17] & SW[1]) | (SW[17] & SW[9]);
    assign LEDG[2] = (~SW[17] & SW[2]) | (SW[17] & SW[10]);
    assign LEDG[3] = (~SW[17] & SW[3]) | (SW[17] & SW[11]);
    assign LEDG[4] = (~SW[17] & SW[4]) | (SW[17] & SW[12]);
    assign LEDG[5] = (~SW[17] & SW[5]) | (SW[17] & SW[13]);
    assign LEDG[6] = (~SW[17] & SW[6]) | (SW[17] & SW[14]);
    assign LEDG[7] = (~SW[17] & SW[7]) | (SW[17] & SW[15]);


This code is simple, but I am trying to optimise it and replace the 8 lines.

I wanted to use some sort of loop, but I failed:

integer index;
   for(index = 0; index < 8; index  = index+1)
       assign LEDG[index] = (~SW[17] & SW[index]) | (SW[17] & SW[index+8]);

I also tried this, and I failed:

//Green leds get the desired byte.
always @(SW) begin
    if (~SW[17])
        assign LEDG = SW[7:0]; 
        assign LEDG = SW[15:5];

I am getting an error saying that the left part of the assignment must have a variable data type.


1 Answer 1


Inside an 'always' block remove the assign, just use LEDG[index] = ... Also, change the output declaration to 'output reg [7:0] LEDG'. The reg data type is the variable data type referenced by the error message.

  • \$\begingroup\$ Can you explain this to me ? Why does it work when I do that? And since this isn't really software programming (where less lines is better), which one of the three codes will be more efficient? \$\endgroup\$
    – JOX
    Jan 18, 2015 at 6:43
  • \$\begingroup\$ An always block indicates a set of procedural instructions that happen in the order they are written. The reg data type can hold on to its value while the rest of the always block is completed, while the 'wire' data type (the default one) does not. Reg is what has to be used in every always block, even though that particular block is short and ends immediately. Assign is used for wire types and can be thought of as connecting physical wires between pieces of hardware, or a path for a signal to travel. \$\endgroup\$
    – DJZygote
    Jan 18, 2015 at 6:52
  • \$\begingroup\$ Thanks, and why doesn't the for loop work? It compiles but the result is not what I want. \$\endgroup\$
    – JOX
    Jan 18, 2015 at 7:02
  • 1
    \$\begingroup\$ I might be off here, but I think 'initial' blocks only execute once, so it will determine the output one time and never update after that. \$\endgroup\$
    – DJZygote
    Jan 18, 2015 at 7:09
  • 1
    \$\begingroup\$ initial is "executed" only once, as you say. \$\endgroup\$ Jan 18, 2015 at 7:48

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