I have a pic32 and I'm talking to a spi nor part to store some data. Now for burst write my flash supports 256 bytes at a time and I want to use my DMA to transfer this. However the part requires that CS stay low for all 256 bytes. I was reading both datasheets and trying to understand CS behavior but I don't quite understand.
I took a look at what happens when I read a status register from the flash which requires me to use DMA to write 4 bytes. On the analyzer I see that CS stays low for the whole transfer which is what I want. But how does it know? There's only one register to write for the spi buffer (not using fifos / enhanced mode). So how the heck does the hardware know I'm not done after the first byte?
My only thought is that there is a buffer you write to, and another buffer that shifts out bits. So if I fill the write buffer before the shift buffer is empty maybe that keeps CS low. I can't prove it though and I'd like to understand how it works before I just blindly use it.