Can sampling I2C influence transmission?

Question

I have 200 kHz I2C communication and I am monitoring it with Logic Analyzer that has 100 kOhm input impedance. When I set sampling rate at 2 Mhz everything looks good on the time diagram. On the other hand, when I set sampling rate at 16 MHz something weird is happening. During start condition my analyzer samples SDA as '0' and SCL as '0' but in next sample it detects SCL as '1'. Everyting looks like there was no start condition and I am not able to debugg my communication.

One more thing I can't understand happens when I set 2 MHz sampling. After end condition my analyzer detects adjacent start condition, end conditon that happens on next sample. I cant fiugre out where it comes from because it doesn't happen at all packets.

There is cleary something wrong with my communication but I am not able to understand what. I2C master is implemented on FPGA (simulating in ISE Simulator has shown that it works properly). On I2C bus I got FPGA, ADAU1772 audio codec (that I am talking to), Atmel EEPROM and equivalent of Saleae Logic Analyzer (used to sample transmission). I have spent 3 days discovering what is going on and now it is just a big headache.

Answer 1

It looks like you're getting some crosstalk between your signals. In your first example, the falling edge of the SDA line is also coupling briefly into the SCK line. In the second example, there may be some other signal coupling into the SDA line.

In order to debug this, you need to switch to an oscilloscope that can show you the analog voltage waveform of these glitches. Preferably one with multiple channels, so that you can simultaneously probe physically adjacent signals and find the correlation between edges and glitches.

Keep in mind that a glitch seen on the logic analyzer may or may not be interpreted as a glitch by the other logic on your board. Also, there may be other glitches that the analyzer isn't picking up, but they are affecting the logic.