Reset of a JK flip flop pulse indicator

Question

I've made a circuit with 74HC109 JK flip flops. The purpose is to catch a pulse from two signals and for about 20 seconds keep the stored value (of which pulse came first). My problem is I need to reset the circuit, both at power up and later on. Unfortunately I don't know how to pull the /CLR lines without wrecking the /Q lines outputs. Grounding them when they are high, I suppose would cause the to draw a lot of current? Is it possible to solve by make a open collector coupling between the /Q and /CLR?

^{simulate this circuit – Schematic created using CircuitLab}

Answer 1

I think using D flip flops with an asynchronous reset input can solve all your problems:

^{simulate this circuit – Schematic created using CircuitLab}

How does this work? Let the top flip flop be A and the bottom one be B.

When you power your circuit you pull \$\overline{RST}\$ down so both flip flops hold zero value, that meaning that \$Q_{A,B}\$ are low an \$\overline{Q}_{A,B}\$ are high.

When A (B) toggles, \$Q_A\$ (\$Q_B\$) goes high because \$D_A=\overline{Q}_B\$ (\$D_B=\overline{Q}_A\$) was high, and of course \$\overline{Q_A}\$ (\$\overline{Q_B}\$) goes low. Now whatever happens to B (A) the circuit can't change state because \$D_B\$ (\$D_A\$) is low. Please note that if something happens to A (B), i.e. another pulse arrives, the circuit indeed changes state.

To reset everything just pull \$\overline{RST}\$ down.

This thing can work if A and B pulses can't come too near in time: i you press both buttons, or press them very fast, what this circuit is going to do is not specified.

Sorry for the ugly schematic but I could not figure out how to depict diagonal wires.

addendum if you need to use jk flip flops, because you have them lying around or because it's an homework question or because you just love jk ffs, you can build a D ff with a JK and a not port:

^{simulate this circuit}

addendum 2: As Jasen pointed out in the comments, for this particular application the not gate isn't necessary since the input signals to the flip flops are available also in the negated form.

Answer 2

This works:

And here are the data files you'll need to run an LTspice simulation if you want to. Download all of the files into the same folder and run the .asc file with LTspice.

Answer 3

You are having problems because JK flipflops aren't the right functional block here. As Vladimir already pointed out, this can be more easily done with D flipflops.

However, another approach to consider is a small microcontroller. It would read all the inputs (only two in your example, but easily expanded to more) often, like every 10 µs. When one is found set, it sets the outputs accordingly and ignores the switch inputs until reset. In the very unlikely event that multiple inputs are found asserted at the same time, just randomly pick one of them.

The timing and logic can now be whatever you want it to be. This method also easily scales to more than two inputs. And, the actual hardware is simpler than a bunch of flipflops. You pretty much just need the micro and its bypass cap. Many micros have internal clocks and the option for internal pullups on some of the input lines. The rest is rather simple firmware.