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I got a code for PN sequence generator using linear feedback shift register in VHDL.

I am using 1010 as a initial seed but in the output all the four PN sequences are 1.

What changes I should do to obtain different PN sequences?

I'm using Xilinx ISE 10.1. This is the code.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

library UNISIM;
use UNISIM.VComponents.all;

entity pnsmall_1 is
  Port (
    clock           : in  STD_LOGIC;                    -- synchronous clock input
    init            : in  STD_LOGIC_vector (3 downto 0);    -- the seed
    pn1,pn2,pn3,pn4 : out STD_LOGIC);                   -- PN sequence
end pnsmall_1;

architecture Behavioral of pnsmall_1 is
  component dp
    port (
      clk,clr,pst,d : in  std_logic;
      q             : out std_logic
    );
  end component;

  component exor
    port (
      a,b : in  std_logic;
      z   : out std_logic
    );
  end component;

  signal q0          : std_logic;   -- 1st stage out
  signal q1          : std_logic;   -- 2nd stage out
  signal q2          : std_logic;   -- 3th stage out
  signal q3          : std_logic;   -- 4th stage out
  signal x           : std_logic;   -- 1st stage input, the feedback
  signal qout        : std_logic_vector(7 downto 0);

begin
  s0: dp port map(
        clk => clock,
        clr => '0',
        pst => init(0),
        d   => x,
        q   => q0
        );
  s1: dp port map(
        clk => clock,
        clr => '0',
        pst => init(1),
        d   => q0,
        q   => q1
        );
  s2: dp port map(
        clk => clock,
        clr => '0',
        pst => init(2),
        d   => q1,
        q   => q2
        );
  s3: dp port map(
        clk => clock,
        clr => '0',
        pst => init(3),
        d   => q2,
        q   => q3
        );

  xx: exor port map(q0,q3,x);

  process(clock)
  begin
    qout(0)<=q3;
    if(clock'event and clock='1') then
      for i in 0 to 6 loop
        qout(i+1)<=qout(i);
      end loop;

      pn1<=qout(1);
      pn2<=qout(3);
      pn3<=qout(5);
      pn4<=qout(7);
    end if;
  end process;
end Behavioral;

the code for dp is below

library IEEE;

use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

library UNISIM; 
use UNISIM.VComponents.all;

-- Code for D FlipFlop with synchronous clear and preset.
entity dp is
   Port (
       clk : in STD_LOGIC; -- synchronous clock
       clr : in STD_LOGIC; -- clear
       pst : in STD_LOGIC; -- preset
       d   : in STD_LOGIC; -- data input
       q   : out STD_LOGIC -- data output
       );
end dp;

architecture Behavioral of dp is
begin
    process(clk,pst,clr) 
      begin 
        if(pst='1')then 
            q<='1';
          elsif(clr='1')then
            q<='0'; 
          elsif (clk'event and clk='1') then 
            q<=d;
        end if;
    end process; 
end Behavioral;
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  • 1
    \$\begingroup\$ Hello, Please indent your code, this is barely readable and will discourage people to read it... \$\endgroup\$ – Blup1980 Jan 21 '15 at 6:16
  • \$\begingroup\$ Indent, and comment your code. Please prefer named instantiation instead of positional instantiation. \$\endgroup\$ – betontalpfa Nov 21 '18 at 13:30
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In addition to all of the issues that Paebbels raises, your immediate problem is that you seem to have misunderstood the function of the pst input of your dp module.

Since you don't show the code for dp, I'm making a lot of assumptions, but if this is a standard D flip-flop module, the clr (clear) and pst (preset) inputs will override the d input whenever they are asserted.

Therefore, two of your dp modules are being forced to '1' at all times by the init vector, and the rest become '1' shortly afterward because of your logic.

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  • \$\begingroup\$ I have attached(edited the question) and added the code of dp.And yes it stands for D flip-flop. \$\endgroup\$ – Dushyanth Shenoy Jan 21 '15 at 13:54
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Xilinx application note 052 describes how to implement such circuits => XAPP052

Besides that, here are some hints and questions for your code:

  • Your Xilinx ISE 10.1 is very outdated. It's from 2008 or so. Current (and last) version is 14.7 from 2013.
  • Please use the ieee.numeric_std library instead of ieee.std_logic_arith and ieee.std_logic_unsigned
  • You aren't using any Xilinx primitives, so you don't need to use unisim.
  • Why are you using self instantiated flip flops (sd) on the one hand and a generic code description on the other hand?
  • Why is your output double registered? Your process describes 13 flip flips. The output of a LFSR is normally registered by it-self.
  • Why are you using odd indices in qout?
  • Have you checked that your polynomial is a generator polynomial and that your init value is a generating element?
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  • \$\begingroup\$ i'm using this for generating code for 4 cdma users. so i need odd indices. i want qout(0) qout(2) qout(4) qout(6) to be containing the outputs of 4 D flipflops. \$\endgroup\$ – Dushyanth Shenoy Jan 21 '15 at 9:02
  • \$\begingroup\$ Might it not be wise to use 4 independent PRNGs (pseudo random number generator) with a higher order polynomial (-> longer cycle type) and different orders? On per user. \$\endgroup\$ – Paebbels Jan 21 '15 at 9:08

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