# VHDL Plus operator + and Downto syntax

Considering variable a and b as STD_LOGIC_VECTOR (31 DOWNTO 0) we have a + b as 33 bit result;

How can we get 32 bits out of this?

Does VHDL have something like (a+b)(31 downto 0) or we should store c:= a+b and then get c(31 downto 0)?

• Are a and b representing signed or unsigned numbers? This is why I don't use slv for arithmetic... – Martin Thompson Jan 21 '15 at 16:53
• they seem to be unsigned, since i did not use signed library. – VSB Jan 21 '15 at 17:23
• It's not recommended to perform arithmetic calculations on STD_LOGIC types. Please use ieee.numeric_std and cast all your operands to SIGNED or UNSIGNED signals with the appropriate length. VHDL does not increase vector sizes to capture potential overflows. If you need $C_{out}$ then expand a and b to 33 bits by concatenation or by using the resize function. – Paebbels Jan 21 '15 at 18:15
• You don't specify which package."+" you use to produce a result with length 33. – user8352 Jan 21 '15 at 23:21
• @VSB - if you don't use a library they are not anything. They are just a bag of bits. VHDL is strongly typed. If you mean something to represnt a number, please use the perfectly good types available for that. Either integer int he basic language or the unsigned and signed vectors from ieee.numeric_std. parallelpoints.com/numbers-in-vhdl – Martin Thompson Jan 22 '15 at 8:31

If a, b, c are of type std_logic_vector(31 downto 0),

then, c := a + b;
will give the 32 bit answer in c (without carry) as you required.

If you want 33 bit answer in c (where c is std_logic_vector(32 downto 0))

Then c := ('0' & a) + ('0' & b) will give the 33 bit answer.

But you will need ieee.std_logic_unsigned package for adding std_logic_vector using + operator.

• Interesting. Personally I'd like to hear why and how this works :) – Dzarda Jan 21 '15 at 14:59
• I think a misunderstanding happend. A(32)+B(32) --> OUT(33) this is due to carry out of add operation, and I want OUT[31..0]. – VSB Jan 21 '15 at 15:11
• @VSB Sorry about the misunderstanding. :) – nidhin Jan 21 '15 at 15:54

declare

signal temp : std_logic_vector(32 downto 0);

and in code

temp <= ('0' & a) + ('0' & b);

c <= temp(31 downto 0);

• With any conventional package, temp <= a + b won't compile. Neither the operators in the non-standard std_logic_unsigned package nor those in the standard numeric_std_unsigned produce an output that is automatically 1 bit larger. – fru1tbat Jan 23 '15 at 13:21