So I've been attempting to create my first development board and layout. I'm first working on the decoupling capacitors, power and ground portions of the layout.

The MCU I'm trying to properly decouple is an STM32F411RET6 running at 100Mhz. According to the STM Application Note a single 0.1uF capacitor at each Vdd pin is adequate. Of course it also says at least one Vdd pin should have a ferrite bead in series with the capacitor. Am I reading this correctly?

I plan the following:

1- 2 layer board

2- Top and bottom layers will have ground pours

3- Components on top layer

4- Traces on both bottom and top as needed

5- Decoupling capacitors sized 0402 .1uF close to pin and 0805 10uF caps further away

I am just a hobbyist trying to create my first micro-controller board and layout and want to make sure I get everything correct before getting too far into things.

Is it worth the additional cost of a four layer board so that I can more easily do proper decoupling by having separate GND and Vdd layer? Or should I stick to two layers and use top layer for GND + traces and the bottom layer Vdd + traces?

The image below ( sorry, created using MS Paint ) is what I hope is a good layout strategy for decoupling capacitors. I'm sure working with 0402 sized caps will be a treat, but it's been suggested a much better size for decoupling caps. The image isn't meant to show proportions or pad sizes properly. Just trying to show my idea for where I want to put the part and traces.

enter image description here

Is this a reasonable layout for decoupling capacitors? Or should I put the capacitor near the pin parallel to the IC instead of perpendicular?

And can anybody recommend a good part number for the decoupling capacitors?

Thanks again, Jim

  • 8
    \$\begingroup\$ You want to read Murata's app manual on decoupling. Directly related to your question, check the section on antiresonance on pg 18 to see why you might want to add 1 uF caps in addition to your 0.1 and 10 uF ones. \$\endgroup\$
    – The Photon
    Commented Jan 22, 2015 at 0:09
  • \$\begingroup\$ +1 for the Murata manual; I had a few pages printed from it lying around on my desk last year but lost them and could never remember where I had got them! \$\endgroup\$ Commented Jan 22, 2015 at 1:11
  • \$\begingroup\$ Seems according to Murata, MLCC 1μF + Ferrite Bead + 10μF works very well. Should I consider such a combination for all 5 power pins of my MCU? \$\endgroup\$
    – Chimera
    Commented Jan 22, 2015 at 1:37
  • \$\begingroup\$ @ThePhoton Thanks for the link. Not being an EE, a lot of that I don't really understand. I'm a lowly software engineer with the ability to do some electronics work. This is by far the most ambitious project to date. I just want to make sure I can build a board that will pass EMI tests if this project makes it off the bench. \$\endgroup\$
    – Chimera
    Commented Jan 22, 2015 at 1:54

3 Answers 3


So you could fill a book with the answer to this question, in fact I think I have some on my shelf

Let’s run through your questions.

Should you use a 4 layer board instead of a 2 layer? I say absolutely yes, the cost argument to going 2 layer is a weak one at best compared to the advantages. Obviously it can be done, and is done, and in this devices case I see they placed VCC and GND right next to each other to make this easier to accomplish. So while I would go 4 layer, you can probably get away with 2 if you want.

Why decouple?

Now without going too deep consider the goal of decoupling your processor. You are trying to supply a stable voltage to it despite the fact that it has dynamic current demands. When your processor is active for instance and its transistors switch they are requesting more current. This current is a change, an increase to the current draw at steady state. Now you have a changing current but where are you going to get that current from?

Well first there’s a little decoupling on the die, but then it tries to pull it through the package power and gnd pins. It wants to get at that capacitor you placed outside of your device but before it gets there it has to travel through the bond wires and or package substrate, out the pins, and down your traces. All of this contributes to the inductance, and ultimately the impedance of the path from the die inside the chip to the capacitor.

Why does this matter? Well because an inductor “resists” changes in current consequently its impedance increases as frequency increases. That’s a simplification, but what happens when you try to drag that change in current through your package and routing is that the inductance limits the amount of current you can get.
So your goal when placing your decoupling capacitors should always be to minimize the impedance, and thus the inductance from the pin to your cap. Now with a QFP package like this you may find the shortest possible connection is right at the pins, with a 4 layer board and a BGA it might be directly underneath, but in practice you can achieve even lower impedance on top layers as well.

Don’t ignore GND either. Current flows in a loop, it does you no good to have a super short path to VCC and long winding path to GND. So if you’re going 2 layer I would put the caps parallel, as close as possible to GND and VCC, route directly to the pins, and then bring power and gnd into the caps. Your goal is to minimize the loop size. More 4 layer arguments and selection

The goal of what we call Power distribution network design is to minimize the impedance across the range of frequencies that your chip will request. To that end having a nice fat GND and VCC plane leading from your caps/part to your regulator will be a much lower impedance path for your lower frequency down to DC. Short of that fat wide traces are recommended if you can.

Cap selection For this processor and your board I think 0.1uF 402s and 0805 10uF are a good choice. The smaller package size helps you have a smaller loop size. I can do 201 by hand, never bought a 1005, but it is easier with a microscope. For more complex designs we select a range of decoupling capacitors to cover the range of frequencies that the part might demand from us. Blindly doing this as in just using 0.1uF, 0.01uF, and 0.001uF as is often suggested can lead to nasty anti resonance peaks giving you high impedance and certain frequencies Again this is a simplification, but I don’t think digging into that here will help you. Interesting to note that placing the 10uF capacitors further away is ok as their role in this design is for the lower frequencies where the impedance caused by the trace inductance will be lower. Also the frequency range you can effectively decouple to is limited by the impedance of the package we discussed earlier.

Actual part selection There are tons of capacitors out there, and usually we don’t make specific part recommendations. But I would look for a 402 0.1uF ceramic capacitor with maybe an X7R temperature coefficient, and a voltage rating double your VCC. Here’s an example of one I have on a BOM

Your questions

OK long winded response I guess but sometimes if you get why something is done it makes it easier to decide how to do it.

So you say:

2 layer board: Seems ok for this, I always prefer a 4 as explained above. There are other benefits such as controlled impedance of traces, less noise, easier to pass emi. I don’t know what your board will do but without reference planes your traces return current will be forced to all follow whatever GND wires it can find. Gets a little messy.

GND pours: Meh it will help balance the copper on top and bottom layers for etching and re-flow, but really you’ll carve it up so much with traces it won’t do you that much good. Better to concentrate on getting power to that chip with as low an impedance as possible. Maybe you can figure out how to run VCC and GND as two copper pours?

Components on top: OK doesn’t really matter, in this case better to have decoupling on top than to go through vias to the bottom. If you are hand assembling it doesn’t really matter, but it would be cheaper to manufacture.

Traces on top and bottom: Definitely you probably won’t get away without this.

Decoupling: I talked about this at length.

Ah what else oh the ferrite, I didn’t see that in the app note. I’m assuming maybe it’s used to isolate one of the more sensitive VCC pins, maybe a PLL or an ADC. And it actually goes VCC supply -> Ferrite -> VCC Pin, with the cap from VCC pin to GND? If so that makes sense it’s probably just a little filter.

Got any questions? Just ask, it's hard to put everything you need to know about decoupling in one answer but hopefully this helps.

  • \$\begingroup\$ Thanks much... I appreciate the thorough answer. I select an answer within the next couple of days to give others a chance to answer... again, thank you very much. \$\endgroup\$
    – Chimera
    Commented Jan 26, 2015 at 18:18

If you are doing this as a hobbyist - and I don't wish to patronise in the slightest - 0402 caps are REALLY small. They require patience, steady hands, and the ability not to sneeze anywhere near your open bag of capacitors because you will blow every single one to every corner of your room. And yes, I've done that.

If you're getting it all assembled for you then of course it's ther problem not yours.

What I tend to do with 4-32MHz devices (PICs, typically) is switch the cap to the underside of the board. I haven't had to worry about heat so far, allowing me to use the space on the bottom layer as I please. I usually place a via on the inner or outer edge of the IC pads, which passes straight through to the the enlarged pad of an 0805 or, if I'm desperate for space, 0603 cap. If you stagger the orientation of the caps you can alternate the ground pin between 'facing toward' and 'facing away from' the IC, such that you have a straight ground trace running along the underside of the pins with caps jutting out from it. This helps minimise the risk of soldering two adjoining caps such that they end up shorting, because you've got a gap between each anode.

From looking at other circuit boards from mass-produced consumer electronics products with microcontrollers at clock frequencies similar to yours, it appears the norm is to place an 0805 or 0603 as close to the IC pin as possible, on the same layer, with a via underneath that connects to whatever trace it needs to on the bottom. In the case of pins used for input or output, the trace usually pops up through a via on the other side of the cap, which attaches straight to the pad of a pull-up resistor. This gives two seamless lines of tightly packed caps and resistors, which saves space but somehow seems... clumsy, at least as far as the overuse of vias goes.

For the proximity caps, 100nF is the standard choice. Ceramic will do; don't waste money on fancy ones. Save your money for some good bead inductors and decoupling caps along the power rails. I recommend a proximity cap on ALL used pins, power or otherwise.

Before you go any further, check the IC manufacturer's documentation. I'd be surprised if they don't mention the subject - you get loads of DOs and DON'Ts in datasheets for precision amplifiers and the like.

  • \$\begingroup\$ Good information and observations here. If you're curious, the reason why capacitor locations seem clumsy is because they are usually some of the last items to go into a design. Commercial designs are usually space constrained to minimize costs. So a router will place all the connectors, chips and route all the major buses and try to shrink the board as part of a layout study. Then they'll try to cram all the other logic, power, caps, test pads, etc. Also, vias are almost free when compared to needing a bigger board or more layers. \$\endgroup\$
    – lm317
    Commented Jan 22, 2015 at 3:42
  • 4
    \$\begingroup\$ Puttings caps on the bottom may substantially increase assembly cost, though you do see it on dense high speed designs. \$\endgroup\$ Commented Jan 22, 2015 at 4:07
  • \$\begingroup\$ I think perhaps with proper magnification 0402 caps should be doable with patience? Perhaps get a solder paste stencil for the board and hot air reflow the board? \$\endgroup\$
    – Chimera
    Commented Jan 26, 2015 at 16:18
  • \$\begingroup\$ Absolutely, if you're capable of doing it then I have no reason to stop you. I will edit my answer shortly to show a little better some methods I have used for my own designs and those which I have come across in the real world. \$\endgroup\$ Commented Jan 26, 2015 at 16:26

When it comes to pad layout for SMT, the basics are we wants solder to evenly fill every area of the component. This ensures good connections and minimal mechanical stress and thus reliability. This is dictated by the surface area and the heating profile. So here are some pointers.

  1. make all pads the same size. In the case of an 0402, you want a symetrical part
    • this ensures we have the same amount of solder on both sides
  2. make the copper connecting the pads equal in width
    • this means heat escapes the pads evenly and both pads heat up at about the same rate
  3. if a pad is connected to a large heat sink, consider adding thermal reliefs in the form of a thinner or longer connecting trace to compensate

There are more advanced routing techniques but the above will get you a board that doesn't have tombstoned parts.

  • \$\begingroup\$ Thanks! The image isn't meant to show proportions or pad sizes properly. Just trying to show my idea for where I want to put the part and traces. \$\endgroup\$
    – Chimera
    Commented Jan 22, 2015 at 0:07

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