I'm working out the exercises in "The Verilog Hardware Description Language" to learn Verilog. I'm currently stuck in exercise 2.7, and since I couldn't find anything on the web about it I thought I'd rather ask here.

I'm implementing this in Vivado and trying to simulate it, but I think the output is always zero. The exercise asks for a description using different techniques of the FSM represented by this circuit:

the circuit of T&M's exercise 2.7

This is my current code for the circuit, which I'm testing with a test bench that correctly simulates a clock with a period of 20 time units.

timescale 1ns / 1ps

module reference(
input Ain,
input Bin,
input Cin,
input rst,
input clk,
output reg Y

reg Q0, Q1;
wire theORW, AandW, BandW;

or #1
    theORG (theORW, AandW, BandW);

and #1
    AandG (AandW, Ain, Q1),
    BandG (BandW, Bin, Q0), 
    YandG (YandW, Cin, theORW);

always @(posedge clk, negedge rst)
        Q0 <= 0;
        Q1 <= 0;
        Y <= 0;
    else begin
        Q0 <= AandW;
        Q1 <= theORW;
        Y <= YandW;


When I simulate the code Y is always 0, no matter what combination of inputs I try and keep high during many clocks. I'm issuing a reset first. Vivado currently builds this RTL representation that looks just like the diagram in the book:

Vivado's RTL representation of the code above

Am I misunderstanding something? Is this the correct behavior of the circuit?

Exercise text:

2.7 Write a description for the FSM shown in Figure 2.7 with inputs Ain, Bin, Cin, clock, and reset, and output Y.

A. A single always block

B. Two always blocks; one for the combinational logic and the other for the sequential.

C. Oops, this circuit is too slow. We can’t have three gate delays between the flip flop outputs and inputs; rather only two. Change part B so that Y is a combinational output, i.e. Move the gate generating d2 to the other side of the flip flops.

D. Simulate all of the above to show that they are all functionally equivalent.


  • \$\begingroup\$ Show us the simulation waveforms, including all of the inputs and outputs. \$\endgroup\$ – Dave Tweed Jan 22 '15 at 2:40
  • \$\begingroup\$ These are the signals, the top ones are from the testbench and from the second Ain downwards it's inside the module. Signals hosted in imgur. \$\endgroup\$ – Peter Jan 22 '15 at 2:53
  • \$\begingroup\$ Without even reading your code: Does this book have a never and revised edition? Typos can happen... \$\endgroup\$ – Sasszem Jul 8 at 2:36

Just from inspecting the logic diagram, I don't see how the original FSM can ever get out of its initial state {Y,Q1,Q0}=3'b000, regardless of its inputs. Are you sure 3'b000 is the correct initial/reset state?

When Q1 is 0, the Ain input is effectively disabled, because anything AND 0 is 0.

Similarly, when Q0==0 the Bin input is disabled, and when {Q1,Q0}==2'b00 the Cin input is disabled. So when the initial state sets Y, Q1, and Q0 all 0, the circuit becomes insensitive to all three of its inputs.

One other thing: the test bench would be more useful to you, if it tested various combinations of the inputs.

| improve this answer | |
  • \$\begingroup\$ Even if the initial state has either Q0, Q1, or both, on 1, after either Ain or Bin go down the FSM is stuck again isn't it? I'll improve the testbench just to spend some more time with Vivado and skip to some exercise I like better or to the next chapter. Thanks! \$\endgroup\$ – Peter Jan 22 '15 at 13:15

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.