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Can i reuse pins DATA0 & DCLK in my application as FPGA SPI interface after configuration (PS) has been completed ?

This are the dual purpose pin options:

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if i set "use as Regular I/O" , i will be able to configure after power on the FPGA, once PS configuration is done , i could use this pins as SPI DATA and Clock .... but not reconfigure de FPGA until next boot...right?

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  • \$\begingroup\$ What does the data sheet say? Will quartus let you assign them (less reliable without actually testing it) \$\endgroup\$ – Chris Stratton Jan 22 '15 at 16:19
  • \$\begingroup\$ quartus lets me do it , but i had to modify the "dual-purpose pin" from: configuration pin to regular I/O.... i just dont know if it will work... \$\endgroup\$ – Cristian Mardones Jan 22 '15 at 16:29
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These settings take effect AFTER configuration completes. So they will behave as configuration pins while the FPGA is being configured, then control will be turned over to your design after configuration is complete. I presume if you reset the whole FPGA back to an unconfigured state, the pins will revert back to configuration pins to reload the design. IOW, this should work fine and allow you to use the pins in your design to access the configuration SPI bus.

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