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On the diagram below, there are 4 PNP transistors.

When RA0 is set to HIGH, then current flows from +5V through RA0 to GND and from +5V through 7 segment display, then through (for example) RB0 (if it's set to HIGH) to GND. Is that right? Is setting a processor pin to HIGH state means the pin will allow current flow from the voltage source to GND through itself?

enter image description here

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One of RA0 - RA3 must be set low, to select the digit, with the other RAx's set high.

RB0 - RB7 must be set low for the segments you want lit in that digit, and set high for the segments that should be off.

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With PNP transistors, the base must be pulled low relative to the emitter in order to turn on. As such, RA1 through RA3 must be pulled high and RA0 must be pulled low in order to activate only the fourth display.

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  • \$\begingroup\$ I see. Will the current from 5V flow through RA0 via the transistor? \$\endgroup\$ – pedro Jan 22 '15 at 22:52
  • \$\begingroup\$ Very little of it. The calculations for the base resistor of a NPN transistor apply to a PNP transistor as well. \$\endgroup\$ – Ignacio Vazquez-Abrams Jan 22 '15 at 22:54
  • \$\begingroup\$ When RA0 is low, it will turn on the transistor, allowing current to flow from +5 V, through the transistor, and through any LED segments connected to a Low RB pin. A small base current will also flow from +5 V through the transistor's emitter and base, to the Low RA pin. \$\endgroup\$ – Peter Bennett Jan 22 '15 at 22:56

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