On the diagram below, there are 4 PNP transistors.
When RA0 is set to HIGH, then current flows from +5V through RA0 to GND and from +5V through 7 segment display, then through (for example) RB0 (if it's set to HIGH) to GND. Is that right? Is setting a processor pin to HIGH state means the pin will allow current flow from the voltage source to GND through itself?