Generating pseudo-random numbers with restricted hardware

Question

I have a need to generate a 448-bit value that appears random, for use in a test circuit. The "randomness" of the values is not overly important; the size of the generator hardware is. I am using an FPGA and I have a budget of ~32 logic elements (in Altera lingo, a LE is a LUT plus an FF).

One possible solution that comes to mind would be to make a 32-bit LFSR, and then use some logic functions/combinations of those bits to generate the 448-bit output.

Is there any other clever solution?

Edit: I'm adding some detail because some have pointed out that it is not possible to create a circuit with 448 output bits using only 32 logic elements.

The block I'll be feeding the "random" values does register all 448 bits at its input port. Though I can't touch the VHDL code of that block, the LUTs that feed those registers can be used for combinational logic by the synthesizer. So though it is true I can't create a circuit with 448 output bits using only 32 LUTs, this is not a problem in this particular case, because only the number of registers is a hard limit.

Answer 1

Is there any other clever solution?

If you are limited to 32 registers then you can only have 32 bits of state in your random numbers. Therefore the only thing you can do to expand it out is use some combinational logic to produce the 448 bits that you need.

Generating the 32 bits is (as you surmise) probably most efficiently done using an LFSR.

I would suggest that using some kind of hash function of those bits would be your best bet to getting the least pattern passing through to the 448 bits output, but that might take up too much logic in your destination. It's not clear to me what constraints you have there.