For a hobby project, I have designed a board using the LTC3355 DC/DC regulator to work as a power supply. I am a software engineer by trade, and I am thus totally underequipped to properly design and troubleshoot this circuit. This is one of my first boards, and it is bound to contain nearly all beginner mistakes you can imagine. I have probably chosen a way too complicated circuit for my level of knowledge, but such is life :).

I can provide oscilloscope views of any node of my circuit if anybody can recommend what I need to measure.

This IC has three main functions:

  1. Buck regulator while input power is available
  2. Supercapacitor charger
  3. Boost regulator while input power is unavailable (sourcing current from the supercapacitor).


The datasheet is available here: http://www.linear.com/docs/44566.


I am having two (possibly related) problems with functions 2 (charging) and 3 (boost). The buck functionality works as intended and I get satisfactory efficiency and output stability.

This question intends to focus on the problematic boost functionality, but if the charging gets solved at the same time, all the better.

When I disconnect the input power, and there is low or zero load on the output, the output is regulated just fine (albeit somewhat more noisy than during buck operation) and the supercapacitor charge is used to keep the output voltage.

However, when the load is increased just slightly, to around 50mA, the output voltage drops to approximately 4V, and V_out and V_scap both appear very noisy. V_scap gets oscillations of around 2V peak-to-peak, at a 2V average voltage. The rated maximum current is 1A, so this should be no problem at all.

Secondly, when I connect the EN_CHG pin to +5V (and input power is available), the supercapacitor is not charged at all. No current is drawn from the input either.


  • Input voltage: 7-20V
  • Output voltage: 5V
  • Supercapacitor: 100F, 2.7V
  • No input current limit set resistor.
  • Resistors and capacitors are of size 0805 to simplify hand soldering and to accommodate for routing between pads, keeping the board single sided.
  • Both inductors are shielded and rated for use in switch-mode supplies well above 1Mhz as used by this circuit), and have plenty of current capability.

I have configured the IC very close to the reference design provided in the datasheet, with a few minor differences. The voltage dividers have been altered slightly to give a 5V output (within specs), and a max 2.7V supercapacitor voltage.

My inductors are of the same inductance as the reference design and rated well above the frequency of the regulator.

Reference design
(source: linear.com)

Possible causes

Here are a few possible issues that I am aware of, where I differ from the reference design or datasheet recommendations, which might adversely affect the performance of my circuit:

  1. Contrary to datasheet recommendations, good design practices, and better judgment, I have laid the circuit out on a single-sided PCB, due to the fact that I lack tools for drilling and manufacturing multi-layer PCB:s. However, I haven't run into thermal issues, which the datasheet hints at, but other design aspects are also adversely affected by this choice:
  2. Poor grounding (stemming from point 1) possibly causing all kinds of interference problems. I am guessing this is the most likely culprit.
  3. The feedback pin of the IC is on the opposite side of what it's measuring so I had to use an aerial wire to avoid routing it all around the board. This is suboptimal... A different layer is used for this purpose in the manufacturer's demo board.
  4. Datasheet reference image mentions a supercapacitor between 1 and 50F. I only have a 100F supercapacitor on hand but didn't think this would cause any problems.
  5. Poor soldering skills. The IC and inductors were soldered with hot-air (no exposed leads, and I might have damaged it by excessive heat. I do think all pads have contact and have probed that there are no shorts. The functionality that actually works suggests that they do have contact. The PFOB, RSTB and CPGOOD pins respond on power failure, output going out of regulation, and capacitor losing voltage.
  6. A few of my capacitors are generally of a larger package (all 0805) than the reference circuits, which (I've learned) alters the equivalent circuit, and might change the frequency response of my system.

What I've tried

I have tried adding extra ceramic capacitors between the supercapacitor and ground, as seen in the Linear demo board here (C10 and C11). These capacitors are not present in the datasheet example circuit: Demo board circuit
(source: linear.com)

This did not make any significant difference in keeping the boost regulator in regulation.

The demo board also lists several OPT (optional?) capacitors, that are not in the datasheet reference design. I have not tried putting anything in these places.

Circuit diagram and board layout

I am having problems getting DipTrace to present my board layout in a more readable fashion, for example by showing the components better. For that reason, I also provide a 3d rendering, which gives a complementary view.



Behold, the horror. PCB and its 3-D view:

PCB 3D view

I have tried to keep current paths as fat as possible, and relevant sensitive nodes as small as I can, but the single-sided layout is limiting... The nodes with blue lines are connected by short air wires. Pad 14 and 13 have pull-down resistors to ground to default to PWM-mode, and no charging (not visible in images). The red lines inside L1 are from an "unpoured" copper fill and are not actual copper on the real board.

The exposed bottom pad of the IC is used for ground, and I routed it out by the corners.

The input power is connected to the polygon under label C6 and the ground fill. The supercapacitor is connected to the polygon at label L2 and the ground fill

Final thoughts

I am wondering if it is totally doomed to fail to have this circuit on a single-sided board, while the manufacturer's demo board uses 4 layers, or whether my attempt can be salvaged somehow. The datasheet mentions adjusting the compensation network at pin V_cbst if needed, but I have no idea how to go about doing that, except randomly trying other component values. I'm lacking a wide assortment of capacitor values and will order more if I get any plausible recommendations.


After getting rid of the alligator clip wires, as recommended by Michael Karcher, and tidying up one of the jumper wires, I got some improvements. Previously I could only reach a maximum load of ~130mA, while I can now reach to approximately 350mA. This is still far from the rated 5 A output from the boost converter. However, my goal is ~1 A, which would be at the same level as the buck regulator used when input power is available.

The supercapacitor is now soldered to the board, using about 1 cm of wire to each lead on the capacitor.

The yellow trace is Vout, and the blue trace is Vcap.

At about 0-5 mA of load, this is how the waveform looks, with the switching frequency of 1 Mhz visible. Boost mode, 5mA load:

Boost mode, 5mA load

However, at about 55-60mA the waveform abruptly changes appearance to this, with a frequency closer to 100 kHz. Here, the output voltage still is regulated at approximately 5V. Boost mode, 60mA load:

Boost mode, 60mA load

At the maximum load current I can achieve, at ~350mA, the output voltage has dropped significantly to 4.5V. Boost mode, 350mA load:

Boost mode, 350mA load

  • 2
    \$\begingroup\$ How do you connect the super cap? The voltage of the super cap at your PCB should not oscillate, as these modern super caps have very low internal resistance. An oscillating voltage between SCAP+ and SCAP- looks like a too high impedance in the connection to the super cap. If SCAP+ to SCAP- is stable, but SCAP- to ground is oscillating, the connection between SCAP- and ground is insufficient. Note that the impedance of the connections are to be considered at the switching frequency, so inductance must not be negliged. Add low-ESR caps near the chip to compensate if inductance can't be avoided. \$\endgroup\$ Commented Jan 24, 2015 at 11:56
  • \$\begingroup\$ Good point, that is a likely issue I didn't consider. Since the cap is quite large in relation to the board I connected it with some 60cm long alligator clip wires, which is very long in this context. I'm going to try and see what happens if I connect it as close to the traces as possible. I did try adding up to a 47uF ceramic capacitor on the board between SCAP+ to ground, with no great effect except reducing some lower frequency and lower amplitude oscillations ~100khz. However, can't the noise at that node also be caused by the switching noise messing up the feedback loop? \$\endgroup\$
    – Henrik
    Commented Jan 24, 2015 at 13:57
  • \$\begingroup\$ The length of the wires already is awful, but what makes matters worse is the contact resistance of alligator clips, especially on those 10 cables for 3$ packs. They are plain unusable for anything requiring low impedance (like the input of a switching regulator). Solder to the cap, and use a decent plug to the board at least. 47uF doesn't sound a lot, but it might already solve the issue at low output currents. Switching noise is generated at SW2, but damped by the inductance of L2. At 100kHz, the impedance of L2 should vastly exceed source impedance. \$\endgroup\$ Commented Jan 24, 2015 at 17:40
  • \$\begingroup\$ ... If the feedback loop is upset by your awful source, you can get really bad effects and oscillation, you are completely right. But the feedback acts on how long the individual pulses are, so an unstable loop will generate unstable pulse lengths, but not primarily create noise at the switching frequency. \$\endgroup\$ Commented Jan 24, 2015 at 17:43

2 Answers 2


A very nicely presented 1st question (or 100th or ...).
Lots of detail to assimilate but it all seems relevant and useful if a good answer is to be found. I cannot spend the time needed now on this but will throw in a few comments and see what others have said later.

I spent about 15 minutes just going to and fro over the circuits and layouts and doing some basic sanity checking. I'm sure your rule checking would have eliminated basic errors.

I have NOT tried to work out what your fault may be caused by specifically - and suspect that it may be a hard fault or misthought rather than the design areas touched on below. BUT any of the following may relate.

Have you tried placing the whole PCB on a PCB ground plane? Can help heaps with single sided. May not.

The two unrouted nets shown presumably have wire links added by hand. (If not that would be an easy fix :-) )

A single side board MAY be doable but with such a complex beast with two switchers and the ability for feedback between them you'd need real care, a scope glued to your right hand and some luck. Even a double sided board (which is about as cheap and quick from many board houses) costs much the same.

A problem is (which may have led to a problem that you get) that the IC seems to have pinouts which assume you can route across the IC with ease so that critical current loops have little area. Because you are on 1 layer this is not true and you have several such loops that more or less overlap and seem to invite disaster.

The obvious ones to minimise to start are the two inductor loops p7-L1-p15 and p16&p17-L2-p14.The L1 loop involves an added jumper and how you route this may have an effect.

Noise getting into the feedback dividers can be bad news indeed. I see you have used c5 across R4 as per their circuit but have no cap across R8 - shown as Copt on one of their circuits and not on another. Simplistically this passes fast load transients or noise that affects output into the feedback pin at a greater rate and level than you get from the divider. Presence or absence in SOME designs is life or death.

Draw lines on printouts of the layout with different coloured markers as to where the loops seem likely to be that are used by different processes (Inductor currents, feedback dividers, ...). (Draw on a screen if that works for you - I find paper and markers more powerful). You can then see likely interactions and any loops that have large open front doors for noise / cross coupling to rush in and out of.

More later maybe.

  • \$\begingroup\$ Thank you for the informative comment. I will just note that I have connected the unrouted nets by wires as short as I could make them. I will try the ground plane idea, and see if it makes any difference. Also, note that the both switchers are not enabled simultaneously, and they both use the same feedback circuitry. So the boost part should be possible to look at in isolation. \$\endgroup\$
    – Henrik
    Commented Jan 23, 2015 at 23:57
  • \$\begingroup\$ I soldered a full copper PCB flat against the back of the board, and soldered several connections all around. This had no great effect at all. However, I experimented by putting a small (1uF) ceramic capacitor between Vout and ground at the boost converters diode. Which seemed to cut the output noise by quite a lot, but did not affect the dropping voltage. The manufacturer's demo board has two output capacitors, one at each converters output. My next PCB layout attempt will incorporate a capacitor there, but with a larger capacitance as in the demo board. \$\endgroup\$
    – Henrik
    Commented Jan 25, 2015 at 22:19

If all else fails, you may want to consider using the simpler 2Amp max LT3110 bidirectional buck-boost supercap charger IC instead. It can continue to use power from the caps all the way down to 1 volt. It is available in a 24 pin TSSOP package that can be mounted on small 24-pin DIP breakout adapter available on eBay. Layout may be a lot easier since the breakout PC will have a ground plane under the IC


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