# How do I bias an AC signal for sampling?

I want to sample a 10Vp-p 50Hz sinusoidal signal.

My ADC can only sample between 0V and 5V, so I need to bias the voltage around 2.5V.

I only have a positive 5V power supply.

To do this, I was going to feed the AC signal to a resistor divider so that it will be 5Vp-p, then add a 2.5V DC offset with another resistor divider pair (AC coupling each stage).

However, I'm having trouble with the DC offset, and I'm not sure this is the best approach to do this.

As you can see, my voltage is still negative. How can I get a 5Vp-p signal offset around 2.5V?

Your sine wave isn't 5V peak-to-peak, it's 5V zero-to-peak.

In your simulation, try adding a 50-ohm resistor to ground between R3 and C1.

In the real world you would need to design the circuit so as to mitigate interactions between components, typically by using op-amps as buffers, but for your first pass in a simulator (where you don't care about the amount of virtual current that is going to be consumed by your virtual 50-ohm voltage divider) just adding the resistor is fine.

Of course, if you actually want to work with a 5Vp-p sine wave, then just change the simulated source's amplitude to 2.5V and everything should start working.

• Sorry about that, edited the question. Commented Jan 24, 2015 at 2:34

You need both to raise the mean voltage to 2.5V, and to attenuate the 10Vp-p input to 5Vp-p.

Assuming both your 5V supply and your AC source are low impedance sources, you can combine both functions in the same circuit:

simulate this circuit – Schematic created using CircuitLab

There are two parts to re-scaling your signal so that it falls within the ADC range. The first is the easiest and is based on dividing the voltage. A 20 volt range (-10 to +10) needs to be reduced to less than 5 volts. I say less than so that you have some margin at the top and bottom. Dividing by 5 would give you a 4 volt range.

The second part is, as you say, dealing with the offset. The actual offset you need to end up with would need to place zero volts (0v) of input signal in the middle of the 5 volt range between 0 and +5 Volts. That is a +2.5 volt offset. You can do all the re-scaling back to whatever you want in software after the fact. Here we are only talking about the analogue signal conditioning for your ADC input.

The following summer amplifier would suffice. Note that the Op Amp summing circuit inverts your signal so you need another inverting amplifier to turn it back up the right way.

I have not worried about 'input offset voltage' or other op amp practical considerations. There are general solutions for these. I've just, in the circuit below, outlined the basic idea. That being the use of different individual channel gains for a summing circuit. That is right! The 6.2 Volt zener reference can be amplified by a gain of less than 1 so it becomes 2.5V. This is much more elegant than using a voltage divider.

simulate this circuit – Schematic created using CircuitLab

Note that the total input resistance of your input channel will be about 165k to have a channel gain of 0.2 (20 Volts / 5 Volts). The trim pot will allow you to calibrate your signal.

The DC offset is almost perfect but you could trim it in your software.

Good luck.

• Don't try to do this with passive components. For a couple of 50c Op-Amps, you can have a really good solution. Commented Jan 24, 2015 at 6:08

@user_1818839 has given an excellent least-parts-count answer.
If the 50 Hz AC signal source comes from a current transformer, the burden resistor could be combined with the two voltage-dividers. But if for example a $$\100\Omega\$$ burden resistor is required as a load for the current transformer, two $$\50\Omega\$$ resistors would be required: likely too much DC current would flow. So it would be better to keep the burden resistor separate:

simulate this circuit – Schematic created using CircuitLab

Let's look at how accuracy might be enhanced:

• Resistors have finite tolerance
• ADC may have offset, magnitude error

The +5V REF voltage should be connected to ADC reference input. In some ADCs, this may be generated by the ADC itself or may be the chip's Vdd DC supply. V_REF should be well-filtered and smooth at the measurement frequency of 50 Hz.
In the second circuit, the 10k resistor tolerance causes a potential DC offset, which combines with ADC's internal DC offset...so the expected +2.5V average voltage may not correspond to the ADC's output code of half_Vref.
A scaling error also exists because those 10k resistors appear in parallel with R3 (burden resistor), reducing its effective value by about 2%.

The DC offset error might best be mitigated with software. By sampling at 4X desired frequency (in this case, sample 200 samples-per-second for 50 Hz input), one can use quadrature arithmetic to derive amplitude of the sinusoidal voltage. Any DC offset disappears in the following subtractions (but be aware that ADC linearity error still appears):

• in_phase component = sample3-sample1
• sinusoidal peak amplitude = $$\\sqrt{{in phase}^2 + {quadrature}^2}\$$