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I have some Microchip (SMSC) LAN9303 Ethernet switches in my system. The LAN9303 is a 3-port switch which has 2 connections for twisted pair cables and one MII connection. The switch chips are some distance apart and each is connected to an FPGA which in turn is connected to a very high data rate link.

The idea was to link the switches via their MII ports so that equipment plugged into switch 1 could talk to switch 2. To do this one LAN9303 was set up as an MII Phy and the other as an MII MAC. Thus one switch thought it was a mac talking to a phy, and the other switch thought it was a PHY talking to a MAC. This worked ok.

Now, to save pins, the LAN9303s have been connected using RMII. As the LAN9303 can only operate as a RMII PHY (not a MAC) I have 2 RMII PHYs connected together. They're just connected with wires at the moment (about 20mm long), as I want to get them working like this on the bench before connecting into the larger system.

The LAN9303 allows the RMII clock to be an input or an output, so I have one switch providing the clock as an output and the other has the clock as an input. This seems to be working OK.

I've tried to read up on this but I've had trouble finding out much what the data coming in to and out of an RMII phy should look like and whether the data it expects to see from a MAC looks like the data is sends out to an RMII MAC?

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    \$\begingroup\$ RMII is like RGMII only a DDR version of MII and GMII, respectively. IEEE 802.3 defines several clauses for (Fast) Ethernet. There are media dependent protocols for Copper/Twisted-Pair (100 BASE-T) or optical wire and also a standard for the chaining of PCS cores (100 BASE-X) -> that's what you are looking for. Note: there is always a master (mac) and a slave (pcs). So if you want to connect 2 phys / macs by RMII/RGMII one has to play a slave role. \$\endgroup\$ – Paebbels Jan 30 '15 at 5:06
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So it turns out an RMII Phy can talk to another RMII phy like this but the LAN9303 can't be connected directly to another LAN9303 as described. The problem is that timing of the DV D0 and D1 signals coming out of one LAN9303 don't meet the requirements for DV D0 and D1 going into the other. The data needs to be moved to the opposite clock edge for this approach to work.

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