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Spartan 6 clocking resources. The link here refers to the clocking resources of spartan-6 FPGA. I am using the DCM-CLKGEN primitive described in the link, to generate a 8x clock based on an input clock. It works fine as long as the input clock is stable.

But now i sweep the input clock at every 90 us by ±5%. I see that although the DCM does not lose lock, it takes very long (15 to 20 us) to change the output freq after changing the input frequency. This is for me undesirable. Any suggestions?

This question was posted on the xilinx forum and the suggestion was to reset the DCM everytime it loses lock. But the problem is that the DCM is not losing lock

Also, this was earlier posted on stackoverflow and now has been reposted here.

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  • \$\begingroup\$ That's an interesting problem. I thought that input clock stability is the requirement. One of the Xilinx reps told me that the good clock should be 45ps p-p. \$\endgroup\$
    – Nazar
    Jan 28, 2015 at 15:15
  • \$\begingroup\$ @Naz Thanks...the input clock is stable, but is jumping frequency every 90 us. And I am sorry I did not understand the 45ps p-p requirement. Are you talking about rise or fall times? \$\endgroup\$
    – Sai Gautam
    Jan 28, 2015 at 15:37
  • \$\begingroup\$ I meant clock jitter, check this out. What do you mean by "jumping frequency every 90us"? \$\endgroup\$
    – Nazar
    Jan 28, 2015 at 15:54
  • \$\begingroup\$ @Naz lets say I start at 13.56 Mhz of input frequency, I then jump to 14.238Mhz after 90us, then to 12.88Mhz after 90 us, and so on. So in effect, I do a frequency modulation of my input frequency in a range of 13.56Mhz +/-5% \$\endgroup\$
    – Sai Gautam
    Jan 28, 2015 at 15:56
  • \$\begingroup\$ What is your intention to change the frequency in such a big range? For example SATA SSC (Spread Spectrum Clocking) uses only 5,000 ppm (0.5 %). A DCM lock can take up to 5 ms! \$\endgroup\$
    – Paebbels
    Jan 28, 2015 at 18:59

3 Answers 3

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I am new to FPGAs, but I do not think this is the way to do it. From what I know, the main clock frequency should not change. If you want to use a part of FPGA as a asynchronous logic block, try to implement the clock divider by yourself toggling the slower clock on the rising edge process of the faster clock. Thus,

architecture
signal mainDiv2: sdt_logic;
signal mainDiv4: sdt_logic;
signal mainDiv8: sdt_logic;
begin
proc1: process(mainCLK)
begin
  if rising_edge(mainCLK) then mainDiv2 = not mainDiv2;
  end if;
end process proc1;

proc2: process(mainDiv2)
begin
  if rising_edge(mainDiv2) then mainDiv4 = not mainDiv4;
  end if;
end process proc2;

proc3: process(mainDiv4)
begin
  if rising_edge(mainDiv4) then mainDiv8 = not mainDiv8;
  end if;
end process proc3;

I have no idea if this will work. You should explore more on how to implement an FPGA for your particular application instead of trying to fix something that might be wrong to begin with. Let me know how it goes.

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  • \$\begingroup\$ However, if main clock get's locked-in automatically, you will have the same problem. Then, implementing a simple counter, as Dave Tweed suggested, is probably the way to go. \$\endgroup\$
    – Nazar
    Jan 28, 2015 at 21:25
  • \$\begingroup\$ The problem with counters is that I cannot multiply my clock. My DCM gives an Fout = Fin x 8 \$\endgroup\$
    – Sai Gautam
    Jan 29, 2015 at 8:22
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The DCM is optimized to provide a stable clock to the logic fabric. It isn't designed to deal with a modulated input frequency. On page 59 in the Spartan 6 DC and Switching Characteristics Datasheet you'll find these specs:

enter image description here

This question was posted on the xilinx forum and the suggestion was to reset the DCM everytime it loses lock. But the problem is that the DCM is not losing lock

Can you reset the DCM every time you change the input frequency? Be aware that after resetting the DCM it probably still takes many us to regain lock.

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  • \$\begingroup\$ You got that right. Thats what I tried testing and the problem is that the DCM cannot be reset under any circumstances as it creates a schort circuit at the transistors \$\endgroup\$
    – Sai Gautam
    Jan 29, 2015 at 8:20
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The on-chip PLLs and DLLs of an FPGA are designed specifically to provide stable, low-jitter clocks to the internal logic, even if the external reference is not all that good. As such, the loop bandwidth is made as narrow as possible for maximum jitter attenuation, within the constraints of an on-chip implementation. They are NOT designed to be frequency-agile in the way that you are trying to use them.

If you just need to divide an input clock by 8, you shouldn't be using a DCM at all. All you need is a simple counter implemented in the fabric.

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  • \$\begingroup\$ According to the doc linked by OP, the DCM in the Spartan 6 is DLL-based, not PLL. There are also PLL's, but it appears OP is using the DLL instead. \$\endgroup\$
    – The Photon
    Jan 28, 2015 at 21:44
  • \$\begingroup\$ @ThePhoton: It doesn't matter, the issues related to the control loop bandwidth and the suitability to the application at hand are still relevant. \$\endgroup\$
    – Dave Tweed
    Jan 28, 2015 at 21:56
  • \$\begingroup\$ @ThePhoton you are right the DCM is DLL based and not PLL based. The CMT of Spartan 6 provides 2 DCMs and 1 PLL. \$\endgroup\$
    – Sai Gautam
    Jan 29, 2015 at 8:15
  • \$\begingroup\$ @DaveTweed Thanks I get your point. You mean that the DLL/PLL on-chip is not designed to handle frequency jumps and produce the expected result. But I am trying to multiply my clock and not divide it. As in my Fout=Finx8. I cannot think of simple logics to do this \$\endgroup\$
    – Sai Gautam
    Jan 29, 2015 at 8:16
  • \$\begingroup\$ In that case, you need to edit your question so that it says "8x" instead of "divide-by-8". What do you use the 8x clock for? \$\endgroup\$
    – Dave Tweed
    Jan 29, 2015 at 12:13

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