Spartan 6 DCM unstable clock output

Question

Spartan 6 clocking resources. The link here refers to the clocking resources of spartan-6 FPGA. I am using the DCM-CLKGEN primitive described in the link, to generate a 8x clock based on an input clock. It works fine as long as the input clock is stable.

But now i sweep the input clock at every 90 us by ±5%. I see that although the DCM does not lose lock, it takes very long (15 to 20 us) to change the output freq after changing the input frequency. This is for me undesirable. Any suggestions?

This question was posted on the xilinx forum and the suggestion was to reset the DCM everytime it loses lock. But the problem is that the DCM is not losing lock

Also, this was earlier posted on stackoverflow and now has been reposted here.

Answer 1

I am new to FPGAs, but I do not think this is the way to do it. From what I know, the main clock frequency should not change. If you want to use a part of FPGA as a asynchronous logic block, try to implement the clock divider by yourself toggling the slower clock on the rising edge process of the faster clock. Thus,

architecture
signal mainDiv2: sdt_logic;
signal mainDiv4: sdt_logic;
signal mainDiv8: sdt_logic;
begin
proc1: process(mainCLK)
begin
  if rising_edge(mainCLK) then mainDiv2 = not mainDiv2;
  end if;
end process proc1;

proc2: process(mainDiv2)
begin
  if rising_edge(mainDiv2) then mainDiv4 = not mainDiv4;
  end if;
end process proc2;

proc3: process(mainDiv4)
begin
  if rising_edge(mainDiv4) then mainDiv8 = not mainDiv8;
  end if;
end process proc3;

I have no idea if this will work. You should explore more on how to implement an FPGA for your particular application instead of trying to fix something that might be wrong to begin with. Let me know how it goes.

Answer 2

The DCM is optimized to provide a stable clock to the logic fabric. It isn't designed to deal with a modulated input frequency. On page 59 in the Spartan 6 DC and Switching Characteristics Datasheet you'll find these specs:

This question was posted on the xilinx forum and the suggestion was to reset the DCM everytime it loses lock. But the problem is that the DCM is not losing lock

Can you reset the DCM every time you change the input frequency? Be aware that after resetting the DCM it probably still takes many us to regain lock.

Answer 3

The on-chip PLLs and DLLs of an FPGA are designed specifically to provide stable, low-jitter clocks to the internal logic, even if the external reference is not all that good. As such, the loop bandwidth is made as narrow as possible for maximum jitter attenuation, within the constraints of an on-chip implementation. They are NOT designed to be frequency-agile in the way that you are trying to use them.

If you just need to divide an input clock by 8, you shouldn't be using a DCM at all. All you need is a simple counter implemented in the fabric.